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Searched refs:XSHAL_XT2000_CACHEATTR_BYPASS (Results 1 – 7 of 7) sorted by relevance

/hal_xtensa-2.7.6/zephyr/soc/nxp_imx8/xtensa/config/
Dsystem.h156 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
217 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFFF2222F /* disable caches in bypass mode */ macro
/hal_xtensa-2.7.6/zephyr/soc/sample_controller/xtensa/config/
Dsystem.h156 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
217 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_s1000/xtensa/config/
Dsystem.h145 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
206 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF222F2F /* disable caches in bypass mode */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_apl_adsp/xtensa/config/
Dsystem.h160 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
221 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_18/xtensa/config/
Dsystem.h160 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
221 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_25/xtensa/config/
Dsystem.h160 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
221 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_20/xtensa/config/
Dsystem.h160 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
221 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro