| /hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ |
| D | adi.h | 150 ASSERT(ADIBaseValid(ui32Base)); in ADI8RegWrite()
151 ASSERT(ui32Reg < ADI_SLAVE_REGS); in ADI8RegWrite()
192 ASSERT(ADIBaseValid(ui32Base)); in ADI16RegWrite()
193 ASSERT(ui32Reg < ADI_SLAVE_REGS); in ADI16RegWrite()
233 ASSERT(ADIBaseValid(ui32Base)); in ADI32RegWrite()
234 ASSERT(ui32Reg < ADI_SLAVE_REGS); in ADI32RegWrite()
265 ASSERT(ADIBaseValid(ui32Base)); in ADI8RegRead()
266 ASSERT(ui32Reg < ADI_SLAVE_REGS); in ADI8RegRead()
300 ASSERT(ADIBaseValid(ui32Base)); in ADI16RegRead()
301 ASSERT(ui32Reg < ADI_SLAVE_REGS); in ADI16RegRead()
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| D | i2c.h | 225 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterControl()
226 ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || in I2CMasterControl()
269 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterSlaveAddrSet()
270 ASSERT(!(ui8SlaveAddr & 0x80)); in I2CMasterSlaveAddrSet()
291 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterEnable()
315 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterDisable()
342 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterBusy()
374 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterBusBusy()
403 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterDataGet()
425 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterDataPut()
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| D | udma.h | 365 ASSERT(uDMABaseValid(ui32Base)); in uDMAEnable()
387 ASSERT(uDMABaseValid(ui32Base)); in uDMADisable()
410 ASSERT(uDMABaseValid(ui32Base)); in uDMAErrorStatusGet()
432 ASSERT(uDMABaseValid(ui32Base)); in uDMAErrorStatusClear()
460 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelEnable()
461 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelEnable()
485 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelDisable()
486 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelDisable()
512 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelIsEnabled()
513 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelIsEnabled()
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| D | udma.c | 74 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelAttributeEnable()
75 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelAttributeEnable()
76 ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | in uDMAChannelAttributeEnable()
115 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelAttributeDisable()
116 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelAttributeDisable()
117 ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | in uDMAChannelAttributeDisable()
157 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelAttributeGet()
158 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelAttributeGet()
200 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelControlSet()
201 ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); in uDMAChannelControlSet()
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| D | ioc.c | 102 ASSERT(ui32IOId <= IOID_31); in IOCPortConfigureSet()
103 ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); in IOCPortConfigureSet()
123 ASSERT(ui32IOId <= IOID_31); in IOCPortConfigureGet()
144 ASSERT(ui32IOId <= IOID_31); in IOCIOShutdownSet()
145 ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || in IOCIOShutdownSet()
171 ASSERT(ui32IOId <= IOID_31); in IOCIOModeSet()
172 ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || in IOCIOModeSet()
200 ASSERT(ui32IOId <= IOID_31); in IOCIOIntSet()
201 ASSERT((ui32Int == IOC_INT_ENABLE) || in IOCIOIntSet()
203 ASSERT((ui32EdgeDet == IOC_NO_EDGE) || in IOCIOIntSet()
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| D | timer.h | 236 ASSERT(TimerBaseValid(ui32Base)); in TimerEnable()
237 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || in TimerEnable()
263 ASSERT(TimerBaseValid(ui32Base)); in TimerDisable()
264 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || in TimerDisable()
371 ASSERT(TimerBaseValid(ui32Base)); in TimerEventControl()
372 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || in TimerEventControl()
469 ASSERT(TimerBaseValid(ui32Base)); in TimerPrescaleSet()
470 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || in TimerPrescaleSet()
472 ASSERT(ui32Value < 256); in TimerPrescaleSet()
518 ASSERT(TimerBaseValid(ui32Base)); in TimerPrescaleGet()
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| D | gpio.h | 171 ASSERT( dioNumberLegal( dioNumber )); in GPIO_readDio()
201 ASSERT( dioMask & GPIO_DIO_ALL_MASK ); in GPIO_readMultiDio()
225 ASSERT( dioNumberLegal( dioNumber )); in GPIO_writeDio()
226 ASSERT(( value == 0 ) || ( value == 1 )); in GPIO_writeDio()
257 ASSERT( dioMask & GPIO_DIO_ALL_MASK ); in GPIO_writeMultiDio()
279 ASSERT( dioNumberLegal( dioNumber )); in GPIO_setDio()
304 ASSERT( dioMask & GPIO_DIO_ALL_MASK ); in GPIO_setMultiDio()
325 ASSERT( dioNumberLegal( dioNumber )); in GPIO_clearDio()
350 ASSERT( dioMask & GPIO_DIO_ALL_MASK ); in GPIO_clearMultiDio()
371 ASSERT( dioNumberLegal( dioNumber )); in GPIO_toggleDio()
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| D | i2s.h | 325 ASSERT(I2SBaseValid(ui32Base)); in I2SDisable()
456 ASSERT(I2SBaseValid(ui32Base)); in I2SClockConfigure()
583 ASSERT(I2SBaseValid(ui32Base)); in I2SIntRegister()
617 ASSERT(I2SBaseValid(ui32Base)); in I2SIntUnregister()
673 ASSERT(I2SBaseValid(ui32Base)); in I2SIntEnable()
705 ASSERT(I2SBaseValid(ui32Base)); in I2SIntDisable()
739 ASSERT(I2SBaseValid(ui32Base)); in I2SIntStatus()
795 ASSERT(I2SBaseValid(ui32Base)); in I2SIntClear()
819 ASSERT(I2SBaseValid(ui32Base)); in I2SSampleStampEnable()
839 ASSERT(I2SBaseValid(ui32Base)); in I2SSampleStampDisable()
[all …]
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| /hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ |
| D | adi.h | 152 ASSERT(ADIBaseValid(ui32Base)); in ADI8RegWrite()
153 ASSERT(ui32Reg < ADI_SLAVE_REGS); in ADI8RegWrite()
194 ASSERT(ADIBaseValid(ui32Base)); in ADI16RegWrite()
195 ASSERT(ui32Reg < ADI_SLAVE_REGS); in ADI16RegWrite()
235 ASSERT(ADIBaseValid(ui32Base)); in ADI32RegWrite()
236 ASSERT(ui32Reg < ADI_SLAVE_REGS); in ADI32RegWrite()
267 ASSERT(ADIBaseValid(ui32Base)); in ADI8RegRead()
268 ASSERT(ui32Reg < ADI_SLAVE_REGS); in ADI8RegRead()
302 ASSERT(ADIBaseValid(ui32Base)); in ADI16RegRead()
303 ASSERT(ui32Reg < ADI_SLAVE_REGS); in ADI16RegRead()
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| D | i2c.h | 227 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterControl()
228 ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || in I2CMasterControl()
271 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterSlaveAddrSet()
272 ASSERT(!(ui8SlaveAddr & 0x80)); in I2CMasterSlaveAddrSet()
293 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterEnable()
317 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterDisable()
344 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterBusy()
376 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterBusBusy()
405 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterDataGet()
427 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterDataPut()
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| D | udma.h | 367 ASSERT(uDMABaseValid(ui32Base)); in uDMAEnable()
389 ASSERT(uDMABaseValid(ui32Base)); in uDMADisable()
412 ASSERT(uDMABaseValid(ui32Base)); in uDMAErrorStatusGet()
434 ASSERT(uDMABaseValid(ui32Base)); in uDMAErrorStatusClear()
462 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelEnable()
463 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelEnable()
487 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelDisable()
488 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelDisable()
514 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelIsEnabled()
515 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelIsEnabled()
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| D | udma.c | 76 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelAttributeEnable()
77 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelAttributeEnable()
78 ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | in uDMAChannelAttributeEnable()
117 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelAttributeDisable()
118 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelAttributeDisable()
119 ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | in uDMAChannelAttributeDisable()
159 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelAttributeGet()
160 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); in uDMAChannelAttributeGet()
202 ASSERT(uDMABaseValid(ui32Base)); in uDMAChannelControlSet()
203 ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); in uDMAChannelControlSet()
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| D | ioc.c | 104 ASSERT(ui32IOId <= IOID_31); in IOCPortConfigureSet()
105 ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); in IOCPortConfigureSet()
125 ASSERT(ui32IOId <= IOID_31); in IOCPortConfigureGet()
146 ASSERT(ui32IOId <= IOID_31); in IOCIOShutdownSet()
147 ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || in IOCIOShutdownSet()
173 ASSERT(ui32IOId <= IOID_31); in IOCIOModeSet()
174 ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || in IOCIOModeSet()
202 ASSERT(ui32IOId <= IOID_31); in IOCIOIntSet()
203 ASSERT((ui32Int == IOC_INT_ENABLE) || in IOCIOIntSet()
205 ASSERT((ui32EdgeDet == IOC_NO_EDGE) || in IOCIOIntSet()
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| D | timer.h | 238 ASSERT(TimerBaseValid(ui32Base)); in TimerEnable()
239 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || in TimerEnable()
265 ASSERT(TimerBaseValid(ui32Base)); in TimerDisable()
266 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || in TimerDisable()
373 ASSERT(TimerBaseValid(ui32Base)); in TimerEventControl()
374 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || in TimerEventControl()
471 ASSERT(TimerBaseValid(ui32Base)); in TimerPrescaleSet()
472 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || in TimerPrescaleSet()
474 ASSERT(ui32Value < 256); in TimerPrescaleSet()
520 ASSERT(TimerBaseValid(ui32Base)); in TimerPrescaleGet()
[all …]
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| D | gpio.h | 174 ASSERT( dioNumberLegal( dioNumber ));
204 ASSERT( dioMask & GPIO_DIO_ALL_MASK );
228 ASSERT( dioNumberLegal( dioNumber ));
229 ASSERT(( value == 0 ) || ( value == 1 ));
260 ASSERT( dioMask & GPIO_DIO_ALL_MASK );
282 ASSERT( dioNumberLegal( dioNumber ));
307 ASSERT( dioMask & GPIO_DIO_ALL_MASK );
328 ASSERT( dioNumberLegal( dioNumber ));
353 ASSERT( dioMask & GPIO_DIO_ALL_MASK );
374 ASSERT( dioNumberLegal( dioNumber ));
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| D | i2s.h | 327 ASSERT(I2SBaseValid(ui32Base)); in I2SDisable()
458 ASSERT(I2SBaseValid(ui32Base)); in I2SClockConfigure()
585 ASSERT(I2SBaseValid(ui32Base)); in I2SIntRegister()
619 ASSERT(I2SBaseValid(ui32Base)); in I2SIntUnregister()
675 ASSERT(I2SBaseValid(ui32Base)); in I2SIntEnable()
707 ASSERT(I2SBaseValid(ui32Base)); in I2SIntDisable()
741 ASSERT(I2SBaseValid(ui32Base)); in I2SIntStatus()
797 ASSERT(I2SBaseValid(ui32Base)); in I2SIntClear()
821 ASSERT(I2SBaseValid(ui32Base)); in I2SSampleStampEnable()
841 ASSERT(I2SBaseValid(ui32Base)); in I2SSampleStampDisable()
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| /hal_ti-latest/simplelink/source/ti/devices/cc32xx/driverlib/ |
| D | i2c.c | 114 ASSERT(_I2CBaseValid(ui32Base)); in _I2CIntNumberGet()
177 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterInitExpClk()
240 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveInit()
241 ASSERT(!(ui8SlaveAddr & 0x80)); in I2CSlaveInit()
276 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveAddressSet()
277 ASSERT(!(ui8AddrNum > 1)); in I2CSlaveAddressSet()
278 ASSERT(!(ui8SlaveAddr & 0x80)); in I2CSlaveAddressSet()
322 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterEnable()
347 ASSERT(_I2CBaseValid(ui32Base)); in I2CSlaveEnable()
377 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterDisable()
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| D | uart.c | 154 ASSERT(UARTBaseValid(ulBase)); in UARTParityModeSet()
155 ASSERT((ulParity == UART_CONFIG_PAR_NONE) || in UARTParityModeSet()
189 ASSERT(UARTBaseValid(ulBase)); in UARTParityModeGet()
223 ASSERT(UARTBaseValid(ulBase)); in UARTFIFOLevelSet()
224 ASSERT((ulTxLevel == UART_FIFO_TX1_8) || in UARTFIFOLevelSet()
229 ASSERT((ulRxLevel == UART_FIFO_RX1_8) || in UARTFIFOLevelSet()
268 ASSERT(UARTBaseValid(ulBase)); in UARTFIFOLevelGet()
321 ASSERT(UARTBaseValid(ulBase)); in UARTConfigSetExpClk()
322 ASSERT(ulBaud != 0); in UARTConfigSetExpClk()
412 ASSERT(UARTBaseValid(ulBase)); in UARTConfigGetExpClk()
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| D | timer.c | 99 ASSERT(TimerBaseValid(ulBase)); in TimerEnable()
100 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || in TimerEnable()
128 ASSERT(TimerBaseValid(ulBase)); in TimerDisable()
129 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || in TimerDisable()
188 ASSERT( (ulConfig == TIMER_CFG_ONE_SHOT) || in TimerConfigure()
255 ASSERT(TimerBaseValid(ulBase)); in TimerControlLevel()
256 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || in TimerControlLevel()
292 ASSERT(TimerBaseValid(ulBase)); in TimerControlEvent()
293 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || in TimerControlEvent()
329 ASSERT(TimerBaseValid(ulBase)); in TimerControlStall()
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| D | udma.c | 159 ASSERT((ulChannelNum & 0xffff) < 32); in uDMAChannelEnable()
186 ASSERT((ulChannelNum & 0xffff) < 32); in uDMAChannelDisable()
213 ASSERT((ulChannelNum & 0xffff) < 32); in uDMAChannelIsEnabled()
249 ASSERT(((unsigned long)pControlTable & ~0x3FF) == in uDMAControlBaseSet()
251 ASSERT((unsigned long)pControlTable >= 0x20000000); in uDMAControlBaseSet()
327 ASSERT((ulChannelNum & 0xffff) < 32); in uDMAChannelRequest()
363 ASSERT((ulChannelNum & 0xffff) < 32); in uDMAChannelAttributeEnable()
364 ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | in uDMAChannelAttributeEnable()
436 ASSERT((ulChannelNum & 0xffff) < 32); in uDMAChannelAttributeDisable()
437 ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | in uDMAChannelAttributeDisable()
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| D | wdt.c | 74 ASSERT((ulBase == WDT_BASE)); in WatchdogRunning()
104 ASSERT((ulBase == WDT_BASE)); in WatchdogEnable()
129 ASSERT((ulBase == WDT_BASE)); in WatchdogLock()
155 ASSERT((ulBase == WDT_BASE)); in WatchdogUnlock()
181 ASSERT((ulBase == WDT_BASE)); in WatchdogLockState()
216 ASSERT((ulBase == WDT_BASE)); in WatchdogReloadSet()
244 ASSERT((ulBase == WDT_BASE)); in WatchdogReloadGet()
269 ASSERT((ulBase == WDT_BASE)); in WatchdogValueGet()
307 ASSERT((ulBase == WDT_BASE)); in WatchdogIntRegister()
344 ASSERT((ulBase == WDT_BASE)); in WatchdogIntUnregister()
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| D | gpio.c | 180 ASSERT(GPIOBaseValid(ulPort)); in GPIODirModeSet()
181 ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT)); in GPIODirModeSet()
215 ASSERT(GPIOBaseValid(ulPort)); in GPIODirModeGet()
216 ASSERT(ucPin < 8); in GPIODirModeGet()
268 ASSERT(GPIOBaseValid(ulPort)); in GPIOIntTypeSet()
269 ASSERT((ulIntType == GPIO_FALLING_EDGE) || in GPIOIntTypeSet()
312 ASSERT(GPIOBaseValid(ulPort)); in GPIOIntTypeGet()
313 ASSERT(ucPin < 8); in GPIOIntTypeGet()
362 ASSERT(GPIOBaseValid(ulPort)); in GPIOIntEnable()
402 ASSERT(GPIOBaseValid(ulPort)); in GPIOIntDisable()
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| /hal_ti-latest/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ |
| D | i2c.h | 194 ASSERT(I2CBaseValid(base)); in I2CControllerCommand()
195 ASSERT((cmd == I2C_CONTROLLER_CMD_SINGLE_SEND) || in I2CControllerCommand()
232 ASSERT(I2CBaseValid(base)); in I2CControllerSetTargetAddr()
233 ASSERT(!(targetAddr & 0x80)); in I2CControllerSetTargetAddr()
253 ASSERT(I2CBaseValid(base)); in I2CControllerEnable()
276 ASSERT(I2CBaseValid(base)); in I2CControllerDisable()
302 ASSERT(I2CBaseValid(base)); in I2CControllerBusy()
333 ASSERT(I2CBaseValid(base)); in I2CControllerBusBusy()
361 ASSERT(I2CBaseValid(base)); in I2CControllerGetData()
382 ASSERT(I2CBaseValid(base)); in I2CControllerPutData()
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| D | gpio.h | 145 ASSERT(dioNumberLegal(dioNumber)); in GPIOReadDio()
174 ASSERT(dioMask & GPIO_DIO_ALL_MASK); in GPIOReadMultiDio()
197 ASSERT(dioNumberLegal(dioNumber)); in GPIOWriteDio()
198 ASSERT((value == 0) || (value == 1)); in GPIOWriteDio()
228 ASSERT(dioMask & GPIO_DIO_ALL_MASK); in GPIOWriteMultiDio()
248 ASSERT(dioNumberLegal(dioNumber)); in GPIOSetDio()
272 ASSERT(dioMask & GPIO_DIO_ALL_MASK); in GPIOSetMultiDio()
292 ASSERT(dioNumberLegal(dioNumber)); in GPIOClearDio()
316 ASSERT(dioMask & GPIO_DIO_ALL_MASK); in GPIOClearMultiDio()
336 ASSERT(dioNumberLegal(dioNumber)); in GPIOToggleDio()
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| /hal_ti-latest/simplelink/source/ti/devices/msp432p4xx/driverlib/ |
| D | dma.c | 75 ASSERT((channelNum & 0xffff) < 8); in DMA_enableChannel()
88 ASSERT((channelNum & 0xffff) < 8); in DMA_disableChannel()
101 ASSERT((channelNum & 0xffff) < 8); in DMA_isChannelEnabled()
115 ASSERT(((uint32_t) controlTable & ~0x3FF) == (uint32_t) controlTable); in DMA_setControlBase()
116 ASSERT((uint32_t) controlTable >= 0x20000000); in DMA_setControlBase()
147 ASSERT((channelNum & 0xffff) < 8); in DMA_requestChannel()
160 ASSERT((channelNum & 0xffff) < 8); in DMA_enableChannelAttribute()
161 ASSERT( in DMA_enableChannelAttribute()
213 ASSERT((channelNum & 0xffff) < 8); in DMA_disableChannelAttribute()
214 ASSERT( in DMA_disableChannelAttribute()
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