114     ASSERT(_I2CBaseValid(ui32Base));  in _I2CIntNumberGet()
177     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterInitExpClk()
240     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveInit()
241     ASSERT(!(ui8SlaveAddr & 0x80));  in I2CSlaveInit()
276     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveAddressSet()
277     ASSERT(!(ui8AddrNum > 1));  in I2CSlaveAddressSet()
278     ASSERT(!(ui8SlaveAddr & 0x80));  in I2CSlaveAddressSet()
322     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterEnable()
347     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveEnable()
377     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterDisable()
402     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveDisable()
444     ASSERT(_I2CBaseValid(ui32Base));  in I2CIntRegister()
451     ASSERT(ui32Int != 0);  in I2CIntRegister()
488     ASSERT(_I2CBaseValid(ui32Base));  in I2CIntUnregister()
495     ASSERT(ui32Int != 0);  in I2CIntUnregister()
525     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterIntEnable()
569     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterIntEnableEx()
594     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveIntEnable()
635     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveIntEnableEx()
660     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterIntDisable()
692     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterIntDisableEx()
717     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveIntDisable()
749     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveIntDisableEx()
779     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterIntStatus()
817     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterIntStatusEx()
855     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveIntStatus()
893     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveIntStatusEx()
937     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterIntClear()
984     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterIntClearEx()
1020     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveIntClear()
1060     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveIntClearEx()
1092     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterSlaveAddrSet()
1093     ASSERT(!(ui8SlaveAddr & 0x80));  in I2CMasterSlaveAddrSet()
1121     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterLineStateGet()
1148     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterBusy()
1183     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterBusBusy()
1242     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterControl()
1243     ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) ||  in I2CMasterControl()
1294     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterErr()
1341     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterDataPut()
1367     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterDataGet()
1398     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterTimeoutSet()
1426     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveACKOverride()
1461     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveACKValueSet()
1515     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveStatus()
1541     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveDataPut()
1567     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveDataGet()
1607     ASSERT(_I2CBaseValid(ui32Base));  in I2CTxFIFOConfigSet()
1638     ASSERT(_I2CBaseValid(ui32Base));  in I2CTxFIFOFlush()
1677     ASSERT(_I2CBaseValid(ui32Base));  in I2CRxFIFOConfigSet()
1707     ASSERT(_I2CBaseValid(ui32Base));  in I2CRxFIFOFlush()
1737     ASSERT(_I2CBaseValid(ui32Base));  in I2CFIFOStatus()
1765     ASSERT(_I2CBaseValid(ui32Base));  in I2CFIFODataPut()
1799     ASSERT(_I2CBaseValid(ui32Base));  in I2CFIFODataPutNonBlocking()
1834     ASSERT(_I2CBaseValid(ui32Base));  in I2CFIFODataGet()
1869     ASSERT(_I2CBaseValid(ui32Base));  in I2CFIFODataGetNonBlocking()
1908     ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255));  in I2CMasterBurstLengthSet()
1936     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterBurstCountGet()
1977     ASSERT(_I2CBaseValid(ui32Base));  in I2CMasterGlitchFilterConfigSet()
2014     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveFIFOEnable()
2040     ASSERT(_I2CBaseValid(ui32Base));  in I2CSlaveFIFODisable()