Searched refs:NONSECURE_OFFSET (Results 1 – 9 of 9) sorted by relevance
94 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKGR), // Index 095 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_SSICLKGR), // Index 196 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_UARTCLKGR), // Index 297 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2CCLKGR), // Index 399 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPIOCLKGR), // Index 5100 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SCLKGR) // Index 6106 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKGS), // Index 0107 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_SSICLKGS), // Index 1108 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_UARTCLKGS), // Index 2109 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2CCLKGS), // Index 3[all …]
375 HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS + NONSECURE_OFFSET) = AON_RTC_EVFLAGS_CH0; in AONRTCEventClear()380 HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS + NONSECURE_OFFSET) = AON_RTC_EVFLAGS_CH1; in AONRTCEventClear()385 HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS + NONSECURE_OFFSET) = AON_RTC_EVFLAGS_CH2; in AONRTCEventClear()459 return(HWREG(AON_RTC_BASE + AON_RTC_O_SEC + NONSECURE_OFFSET)); in AONRTCSecGet()491 return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC + NONSECURE_OFFSET)); in AONRTCFractionGet()515 return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC + NONSECURE_OFFSET)); in AONRTCSubSecIncrGet()745 HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP + NONSECURE_OFFSET) = ui32CompValue; in AONRTCCompareValueSet()750 HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP + NONSECURE_OFFSET) = ui32CompValue; in AONRTCCompareValueSet()755 HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP + NONSECURE_OFFSET) = ui32CompValue; in AONRTCCompareValueSet()786 ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP + NONSECURE_OFFSET); in AONRTCCompareValueGet()[all …]
334 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_VDCTL) = ui32Enable; in PRCMMcuUldoConfigure()373 HWREG( PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKDIV ) = clkDiv; in PRCMGPTimerClockDivisionSet()399 return ( HWREG( PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKDIV )); in PRCMGPTimerClockDivisionGet()608 return ((HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? in PRCMLoadGet()642 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN; in PRCMDomainEnable()646 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M; in PRCMDomainEnable()681 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_RFCCLKG) = 0x0; in PRCMDomainDisable()685 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_VIMSCLKG) = 0x0; in PRCMDomainDisable()778 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL0RFC) = 0; in PRCMRfPowerDownWhenIdle()1091 return ((HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDSTAT1RFC) & in PRCMRfReady()
69 currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SEC ); in AONRTCCurrent64BitValueGet()70 currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SUBSEC ); in AONRTCCurrent64BitValueGet()71 ui32SecondSecRead = HWREG( AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SEC ); in AONRTCCurrent64BitValueGet()
136 …ui32Reg = HWREG(AON_PMCTL_BASE + NONSECURE_OFFSET + AON_PMCTL_O_RAMCFG) & ~AON_PMCTL_RAMCFG_BUS_SR… in AONPMCTLMcuSRamRetConfig()138 HWREG(AON_PMCTL_BASE + NONSECURE_OFFSET + AON_PMCTL_O_RAMCFG) = ui32Reg; in AONPMCTLMcuSRamRetConfig()156 return (HWREG(AON_PMCTL_BASE + NONSECURE_OFFSET + AON_PMCTL_O_PWRSTAT)); in AONPMCTLPowerStatusGet()
79 currentOpMode = HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_OPMODEREQ); in AUXSYSIFOpModeChange()80 while ( currentOpMode != HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_OPMODEACK)); in AUXSYSIFOpModeChange()92 HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_OPMODEREQ) = nextMode; in AUXSYSIFOpModeChange()
339 HWREG(AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SYNC); in SysCtrlAonSync()365 HWREG(AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SYNC) = 1; in SysCtrlAonUpdate()366 HWREG(AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SYNC); in SysCtrlAonUpdate()
83 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL1VIMS) = vimsPdMode; in SysCtrlIdle()
50 #define NONSECURE_OFFSET 0x0 macro
