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Searched refs:AUX_DDI0_OSC_BASE (Results 1 – 8 of 8) sorted by relevance

/hal_ti-2.7.6/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/
Dosc.h159 DDI16BitWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE, in OSCXHfPowerModeSet()
181 DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, in OSCClockLossEventEnable()
204 DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, in OSCClockLossEventDisable()
288 return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, in OSCHfSourceReady()
316 … uint16_t hfSrc = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0) & DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M; in OSCHfSourceSwitch()
322 …HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_S… in OSCHfSourceSwitch()
324 HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); in OSCHfSourceSwitch()
334 …HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_S… in OSCHfSourceSwitch()
383 uint16_t regVal = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); in OSC_IsHPOSCEnabledWithHfDerivedLfClock()
Dsetup_rom.c232 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim); in SetupAfterColdResetWakeupFromShutDownCfg2()
237 DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL, in SetupAfterColdResetWakeupFromShutDownCfg2()
247 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2, in SetupAfterColdResetWakeupFromShutDownCfg2()
252 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH2, ui32Trim); in SetupAfterColdResetWakeupFromShutDownCfg2()
254 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH1, ui32Trim); in SetupAfterColdResetWakeupFromShutDownCfg2()
260 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPCTL, ui32Trim); in SetupAfterColdResetWakeupFromShutDownCfg2()
266 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = in SetupAfterColdResetWakeupFromShutDownCfg2()
273 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = in SetupAfterColdResetWakeupFromShutDownCfg2()
280 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim); in SetupAfterColdResetWakeupFromShutDownCfg2()
288 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) = in SetupAfterColdResetWakeupFromShutDownCfg2()
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Dosc.c135 DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, in OSCClockSourceSet()
145 DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, in OSCClockSourceSet()
169 ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, in OSCClockSourceGet()
175 ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, in OSCClockSourceGet()
340 …DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, SetupGetTrimForAnabypassValue1( ccfg_M… in OSC_AdjustXoscHfCapArray()
609 ampValue = ( HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_STAT1 ) & in OSCHF_DebugGetCrystalAmplitude()
629 ampCompTh1 = HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_AMPCOMPTH1 ); in OSCHF_DebugGetExpectedAverageCrystalAmplitude()
Dsetup.c263 …HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_S… in TrimAfterColdResetWakeupFromShutDown()
265 HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); in TrimAfterColdResetWakeupFromShutDown()
Dddi.h142 return(ui32Base == AUX_DDI0_OSC_BASE); in DDIBaseValid()
/hal_ti-2.7.6/simplelink/source/ti/drivers/power/
DPowerCC26X2_calibrateRCOSC.c343 DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, in runCalibrateFsm()
349 DDI16BitfieldRead(AUX_DDI0_OSC_BASE, in runCalibrateFsm()
397 DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, in runCalibrateFsm()
427 DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, in runCalibrateFsm()
434 DDI16BitfieldRead(AUX_DDI0_OSC_BASE, in runCalibrateFsm()
464 DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, in runCalibrateFsm()
471 DDI16BitfieldRead(AUX_DDI0_OSC_BASE, in runCalibrateFsm()
647 (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RCOSCHFCTL) & in calibrateRcoscHf1()
652 (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL) in calibrateRcoscHf1()
657 (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ATESTCTL) in calibrateRcoscHf1()
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DPowerCC26X2.c304 HWREG(AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0) = DDI_0_OSC_CTL0_XTAL_IS_24M; in Power_init()
383 AUX_DDI0_OSC_BASE, in Power_init()
1196 AUX_DDI0_OSC_BASE, in disableLFClockQualifiers()
1213 AUX_DDI0_OSC_BASE, in disableLFClockQualifiers()
1371 …HWREG(AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL) = DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_… in configureXOSCHF()
1375 … HWREG(AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL) = DDI_0_OSC_XOSCHFCTL_TCXO_MODE; in configureXOSCHF()
1451 … HWREG(AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_XOSCHFCTL) = DDI_0_OSC_XOSCHFCTL_TCXO_MODE | in configureXOSCHF()
1456 … HWREG(AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_XOSCHFCTL) = DDI_0_OSC_XOSCHFCTL_TCXO_MODE | in configureXOSCHF()
1496 HWREG(AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL) = DDI_0_OSC_XOSCHFCTL_BYPASS; in switchToTCXO()
/hal_ti-2.7.6/simplelink/source/ti/devices/cc13x2_cc26x2/inc/
Dhw_memmap.h97 #define AUX_DDI0_OSC_BASE 0x400CA000 // DDI macro