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Searched refs:ADI3_BASE (Results 1 – 5 of 5) sorted by relevance

/hal_ti-2.7.6/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/
Dsetup.c251 HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 | in TrimAfterColdResetWakeupFromShutDown()
280 … HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL3 ) = ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST ; in TrimAfterColdResetWakeupFromShutDown()
303 …HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKU… in TrimAfterColdResetWakeupFromShutDown()
305 …HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKU… in TrimAfterColdResetWakeupFromShutDown()
Dsetup_rom.c127 HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & in SetupStepVddrTrimTo()
144 HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = ( in SetupStepVddrTrimTo()
145 … ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) | in SetupStepVddrTrimTo()
178 …HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_… in SetupAfterColdResetWakeupFromShutDownCfg1()
182 HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) = in SetupAfterColdResetWakeupFromShutDownCfg1()
185 …HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_… in SetupAfterColdResetWakeupFromShutDownCfg1()
Dsys_ctrl.c283 …HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 * 2 )) = (( ADI_3_REFSYS_CTL… in SysCtrlSetRechargeBeforePowerDown()
286 HWREGB( ADI3_BASE + ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 ); in SysCtrlSetRechargeBeforePowerDown()
Dadi.h112 return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE || in ADIBaseValid()
/hal_ti-2.7.6/simplelink/source/ti/devices/cc13x2_cc26x2/inc/
Dhw_memmap.h82 #define ADI3_BASE 0x40086200 // ADI macro