Searched refs:REG_ADDR32 (Results 1 – 16 of 16) sorted by relevance
33 #define reg_aes_mode REG_ADDR32(0x1600b0)39 #define reg_embase_addr REG_ADDR32(0x140b04)41 #define reg_aes_irq_mask REG_ADDR32(0x16000c)43 #define reg_aes_irq_status REG_ADDR32(0x160010)45 #define reg_aes_clr_irq_status REG_ADDR32(0x160018)54 #define reg_aes_key(v) REG_ADDR32(0x1600b4+(v*4))56 #define reg_aes_ptr REG_ADDR32(0x1600c4)
34 #define reg_tmr_ctrl32 REG_ADDR32(0x140140)59 #define reg_tmr0_capt REG_ADDR32(0x140144)60 #define reg_tmr1_capt REG_ADDR32(0x140148)61 #define reg_tmr_capt(i) REG_ADDR32(0x140144 + ((i) << 2))67 #define reg_wt_target REG_ADDR32(0x14014c)70 #define reg_tmr0_tick REG_ADDR32(0X140150)71 #define reg_tmr1_tick REG_ADDR32(0X140154)72 #define reg_tmr_tick(i) REG_ADDR32(0X140150 + ((i) << 2))
37 #define reg_pke_ctrl REG_ADDR32(REG_PKE_BASE+0x00)43 #define reg_pke_conf REG_ADDR32(REG_PKE_BASE+0x04)50 #define reg_pke_mc_ptr REG_ADDR32(REG_PKE_BASE+0x10)52 #define reg_pke_stat REG_ADDR32(REG_PKE_BASE+0x20)57 #define reg_pke_rt_code REG_ADDR32(REG_PKE_BASE+0x24)62 #define reg_pke_exe_conf REG_ADDR32(REG_PKE_BASE+0x50)
33 #define reg_system_tick REG_ADDR32(STIMER_BASE_ADDR)35 #define reg_system_irq_level REG_ADDR32(STIMER_BASE_ADDR+0x4)73 #define reg_system_timer_set_32k REG_ADDR32(STIMER_BASE_ADDR+0xc)75 #define reg_system_timer_read_32k REG_ADDR32(STIMER_BASE_ADDR+0x10)77 #define reg_system_cal_latch_32k REG_ADDR32(STIMER_BASE_ADDR+0x14)79 #define reg_system_up_32k REG_ADDR32(STIMER_BASE_ADDR+0x18)
32 #define reg_gpio_pa_setting1 REG_ADDR32(0x140300)38 #define reg_gpio_pa_setting2 REG_ADDR32(0x140304)49 #define reg_gpio_pb_setting1 REG_ADDR32(0x140308)55 #define reg_gpio_pb_setting2 REG_ADDR32(0x14030c)66 #define reg_gpio_pc_setting1 REG_ADDR32(0x140310)73 #define reg_gpio_pc_setting2 REG_ADDR32(0x140314)84 #define reg_gpio_pd_setting1 REG_ADDR32(0x140318)91 #define reg_gpio_pd_setting2 REG_ADDR32(0x14031c)102 #define reg_gpio_pe_setting1 REG_ADDR32(0x140320)108 #define reg_gpio_pe_setting2 REG_ADDR32(0x140324)[all …]
31 #define reg_dma_id REG_ADDR32(0x100400)32 #define reg_dma_cfg REG_ADDR32(0x100410)47 #define reg_dma_ctrl(i) REG_ADDR32(( 0x00100444 +(i)*0x14))98 #define reg_dma_src_addr(i) REG_ADDR32 (( 0x00100448 +(i)*0x14))99 #define reg_dma_dst_addr(i) REG_ADDR32 (( 0x0010044c +(i)*0x14))100 #define reg_dma_size(i) REG_ADDR32 (( 0x00100450 +(i)*0x14))116 #define reg_dma_llp(i) REG_ADDR32 (( 0x00100454 +(i)*0x14))
43 #define reg_trng_rtcr REG_ADDR32(REG_TRNG_BASE+0x04)53 #define reg_rbg_dr REG_ADDR32(REG_TRNG_BASE+0x0c)
109 #define reg_usb_ep8123_ptr REG_ADDR32(0x100810)114 #define reg_usb_ep4567_ptr REG_ADDR32(0x100814)121 #define reg_usb_ep8123_dat REG_ADDR32(0x100818)126 #define reg_usb_ep4567_dat REG_ADDR32(0x10081c)152 #define reg_usb_ep8123_buf_addr REG_ADDR32(0x100828)157 #define reg_usb_ep4567_buf_addr REG_ADDR32(0x10082c)
54 #define reg_mspi_config REG_ADDR32(0x140104)
48 #define reg_ana_addr_data32 REG_ADDR32(ALG_BASE_ADDR+0x04)
40 #define reg_rst REG_ADDR32(0x1401e0)91 #define reg_clk_en REG_ADDR32(0x1401e4)
147 #define reg_rf_access_code REG_ADDR32(REG_BASEBAND_BASE_ADDR+0x08)309 #define reg_rf_timestamp REG_ADDR32(REG_BASEBAND_BASE_ADDR+0x50)588 #define reg_rf_ll_cmd_schedule REG_ADDR32(REG_BB_LL_BASE_ADDR+0x18)682 #define reg_rf_ll_rx_fst_timeout REG_ADDR32(REG_BB_LL_BASE_ADDR+0x28)687 #define reg_rf_ll_fsm_timeout REG_ADDR32(REG_BB_LL_BASE_ADDR+0x2c)692 #define reg_rf_fsm_timeout REG_ADDR32(0x80140a2c)
38 #define reg_uart_data_word_buf(i) REG_ADDR32(reg_uart_data_buf_adr(i)) //uart(i)
156 #define reg_pwm_cycle(i) REG_ADDR32(REG_PWM_BASE+0x14 + (i << 2))
310 #define reg_hspi_addr_32 REG_ADDR32(HSPI_BASE_ADDR+0x10)
72 #define REG_ADDR32(a) (*(volatile unsigned long*)(REG_RW_BASE_ADDR | (a))) macro
