1 /******************************************************************************
2  * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3  * All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *   http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  *****************************************************************************/
18 
19 /********************************************************************************************************
20  * @file	mspi_reg.h
21  *
22  * @brief	This is the header file for B91
23  *
24  * @author	Driver Group
25  *
26  *******************************************************************************************************/
27 #pragma once
28 
29 #include "../sys.h"
30 
31 /*******************************      MSPI registers: 0x140100      ******************************/
32 #define reg_mspi_data       REG_ADDR8(0x140100)
33 
34 #define reg_mspi_fm       	REG_ADDR8(0x140101)
35 enum{
36 	FLD_MSPI_RD_TRIG_EN		=  BIT(0),
37 	FLD_MSPI_RD_MODE		=  BIT(1),
38 	FLD_MSPI_DATA_LINE		=  BIT_RNG(2,3),
39 	FLD_MSPI_CSN			=  BIT(4),
40 };
41 
42 #define reg_mspi_status     REG_ADDR8(0x140102)
43 enum{
44 	FLD_MSPI_BUSY			=  BIT(0),
45 };
46 
47 #define reg_mspi_fm1		REG_ADDR8(0x140103)
48 enum{
49 	FLD_MSPI_TIMEOUT_CNT	=  BIT_RNG(0,2),
50 	FLD_MSPI_CS2SCL_CNT		=  BIT_RNG(3,4),
51 	FLD_MSPI_CS2CS_CNT		=  BIT_RNG(5,7),
52 };
53 
54 #define reg_mspi_config	    REG_ADDR32(0x140104)
55 #define reg_mspi_set_l		REG_ADDR8(0x140104)
56 enum{
57 	FLD_MSPI_MULTIBOOT_ADDR_OFFSET	=  BIT_RNG(0,2),/**<mutiboot address offset option, 0:0k;  1:128k;  2:256k;  4:256k*/
58 };
59 
60 #define reg_mspi_set_h   	REG_ADDR8(0x140105)
61 enum{
62 	FLD_MSPI_PROGRAM_SPACE_SIZE		=  BIT_RNG(0,6),/**< program space size = mspi_set_h*4k*/
63 };
64 #define reg_mspi_xip_config	REG_ADDR16(0x140106)
65 #define reg_mspi_cmd_ahb   	REG_ADDR8(0x140106)
66 enum{
67 	FLD_MSPI_RD_CMD			=  BIT_RNG(0,7), /**< xip read command */
68 };
69 
70 #define reg_mspi_fm_ahb   	REG_ADDR8(0x140107)
71 enum{
72 	FLD_MSPI_DUMMY			=  BIT_RNG(0,3),/**< dummy cycle = FLD_MSPI_DUMMY + 1 */
73 	FLD_MSPI_DAT_LINE		=  BIT_RNG(4,5),/**< 0:single line;  1: dual line;  2:quad line; 3:quad line */
74 	FLD_MSPI_ADDR_LINE		=  BIT(6),      /**< 0:single line;   1:the same to dat_line_h */
75 	FLD_MSPI_CMD_LINE		=  BIT(7),      /**< 0:single line;   1:the same to dat_line_h */
76 };
77 
78 
79