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/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_pwr_ex.h724 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ argument
725 ((TYPE) == PWR_PVM_2) ||\
726 ((TYPE) == PWR_PVM_3) ||\
727 ((TYPE) == PWR_PVM_4))
729 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\ argument
730 ((TYPE) == PWR_PVM_3) ||\
731 ((TYPE) == PWR_PVM_4))
735 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ argument
736 ((TYPE) == PWR_PVM_3) ||\
737 ((TYPE) == PWR_PVM_4))
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Dstm32l4xx_hal_cortex.h349 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
350 ((TYPE) == MPU_TEX_LEVEL1) || \
351 ((TYPE) == MPU_TEX_LEVEL2) || \
352 ((TYPE) == MPU_TEX_LEVEL4))
354 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
355 ((TYPE) == MPU_REGION_PRIV_RW) || \
356 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
357 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
358 ((TYPE) == MPU_REGION_PRIV_RO) || \
359 ((TYPE) == MPU_REGION_PRIV_RO_URO))
Dstm32l4xx_hal_ospi.h880 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ argument
881 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \
882 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \
883 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
885 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ argument
886 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \
887 ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \
888 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \
889 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
910 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ argument
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Dstm32l4xx_hal_mmc.h391 #define IS_MMC_ERASE_TYPE(TYPE) (((TYPE) == HAL_MMC_ERASE) || \ argument
392 ((TYPE) == HAL_MMC_TRIM) || \
393 ((TYPE) == HAL_MMC_DISCARD) || \
394 ((TYPE) == HAL_MMC_SECURE_ERASE) || \
395 ((TYPE) == HAL_MMC_SECURE_TRIM_STEP1) || \
396 ((TYPE) == HAL_MMC_SECURE_TRIM_STEP2))
410 #define IS_MMC_SRT_TYPE(TYPE) (((TYPE) == HAL_MMC_SRT_ERASE) || \ argument
411 ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_ERASE) || \
412 ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM) || \
413 ((TYPE) == HAL_MMC_SRT_VENDOR_DEFINED))
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_xspi.h1026 #define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \ argument
1027 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \
1028 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \
1029 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \
1030 ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \
1031 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS))
1127 #define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ argument
1128 ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \
1129 ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \
1130 ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG))
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/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_cortex.h348 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
349 ((TYPE) == MPU_TEX_LEVEL1) || \
350 ((TYPE) == MPU_TEX_LEVEL2) || \
351 ((TYPE) == MPU_TEX_LEVEL4))
353 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
354 ((TYPE) == MPU_REGION_PRIV_RW) || \
355 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
356 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
357 ((TYPE) == MPU_REGION_PRIV_RO) || \
358 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_xspi.h1062 #define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \ argument
1063 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \
1064 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \
1065 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \
1066 ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \
1067 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS))
1166 #define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ argument
1167 ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \
1168 ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \
1169 ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG))
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/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_cortex.h317 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
318 ((TYPE) == MPU_TEX_LEVEL1) || \
319 ((TYPE) == MPU_TEX_LEVEL2))
321 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
322 ((TYPE) == MPU_REGION_PRIV_RW) || \
323 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
324 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
325 ((TYPE) == MPU_REGION_PRIV_RO) || \
326 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_cortex.h317 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
318 ((TYPE) == MPU_TEX_LEVEL1) || \
319 ((TYPE) == MPU_TEX_LEVEL2))
321 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
322 ((TYPE) == MPU_REGION_PRIV_RW) || \
323 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
324 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
325 ((TYPE) == MPU_REGION_PRIV_RO) || \
326 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_hal_cortex.h318 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
319 ((TYPE) == MPU_TEX_LEVEL1) || \
320 ((TYPE) == MPU_TEX_LEVEL2))
322 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
323 ((TYPE) == MPU_REGION_PRIV_RW) || \
324 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
325 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
326 ((TYPE) == MPU_REGION_PRIV_RO) || \
327 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_cortex.h317 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
318 ((TYPE) == MPU_TEX_LEVEL1) || \
319 ((TYPE) == MPU_TEX_LEVEL2))
321 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
322 ((TYPE) == MPU_REGION_PRIV_RW) || \
323 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
324 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
325 ((TYPE) == MPU_REGION_PRIV_RO) || \
326 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_cortex.h309 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
310 ((TYPE) == MPU_TEX_LEVEL1) || \
311 ((TYPE) == MPU_TEX_LEVEL2))
313 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
314 ((TYPE) == MPU_REGION_PRIV_RW) || \
315 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
316 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
317 ((TYPE) == MPU_REGION_PRIV_RO) || \
318 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_xspi.h1095 #define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \ argument
1096 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \
1097 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \
1098 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \
1099 ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \
1100 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS))
1195 #define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ argument
1196 ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \
1197 ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \
1198 ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG))
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/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_cortex.h336 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
337 ((TYPE) == MPU_TEX_LEVEL1) || \
338 ((TYPE) == MPU_TEX_LEVEL2))
340 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
341 ((TYPE) == MPU_REGION_PRIV_RW) || \
342 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
343 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
344 ((TYPE) == MPU_REGION_PRIV_RO) || \
345 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_hal_cortex.h346 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
347 ((TYPE) == MPU_TEX_LEVEL1) || \
348 ((TYPE) == MPU_TEX_LEVEL2))
350 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
351 ((TYPE) == MPU_REGION_PRIV_RW) || \
352 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
353 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
354 ((TYPE) == MPU_REGION_PRIV_RO) || \
355 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_cortex.h338 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
339 ((TYPE) == MPU_TEX_LEVEL1) || \
340 ((TYPE) == MPU_TEX_LEVEL2))
342 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
343 ((TYPE) == MPU_REGION_PRIV_RW) || \
344 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
345 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
346 ((TYPE) == MPU_REGION_PRIV_RO) || \
347 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_hal_cortex.h324 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
325 ((TYPE) == MPU_TEX_LEVEL1) || \
326 ((TYPE) == MPU_TEX_LEVEL2))
328 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
329 ((TYPE) == MPU_REGION_PRIV_RW) || \
330 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
331 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
332 ((TYPE) == MPU_REGION_PRIV_RO) || \
333 ((TYPE) == MPU_REGION_PRIV_RO_URO))
Dstm32mp1xx_hal_fdcan.h2136 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ argument
2137 ((TYPE) == FDCAN_FILTER_DUAL ) || \
2138 ((TYPE) == FDCAN_FILTER_MASK ))
2139 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ argument
2140 ((TYPE) == FDCAN_FILTER_DUAL ) || \
2141 ((TYPE) == FDCAN_FILTER_MASK ) || \
2142 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
2143 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ argument
2144 ((TYPE) == FDCAN_REMOTE_FRAME))
2217 #define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \ argument
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/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_cortex.h338 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
339 ((TYPE) == MPU_TEX_LEVEL1) || \
340 ((TYPE) == MPU_TEX_LEVEL2))
342 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
343 ((TYPE) == MPU_REGION_PRIV_RW) || \
344 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
345 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
346 ((TYPE) == MPU_REGION_PRIV_RO) || \
347 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_cortex.h338 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
339 ((TYPE) == MPU_TEX_LEVEL1) || \
340 ((TYPE) == MPU_TEX_LEVEL2))
342 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
343 ((TYPE) == MPU_REGION_PRIV_RW) || \
344 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
345 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
346 ((TYPE) == MPU_REGION_PRIV_RO) || \
347 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_cortex.h339 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
340 ((TYPE) == MPU_TEX_LEVEL1) || \
341 ((TYPE) == MPU_TEX_LEVEL2))
343 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
344 ((TYPE) == MPU_REGION_PRIV_RW) || \
345 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
346 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
347 ((TYPE) == MPU_REGION_PRIV_RO) || \
348 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_hal_cortex.h363 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
364 ((TYPE) == MPU_TEX_LEVEL1) || \
365 ((TYPE) == MPU_TEX_LEVEL2))
367 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
368 ((TYPE) == MPU_REGION_PRIV_RW) || \
369 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
370 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
371 ((TYPE) == MPU_REGION_PRIV_RO) || \
372 ((TYPE) == MPU_REGION_PRIV_RO_URO))
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_cortex.h372 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ argument
373 ((TYPE) == MPU_TEX_LEVEL1) || \
374 ((TYPE) == MPU_TEX_LEVEL2))
376 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ argument
377 ((TYPE) == MPU_REGION_PRIV_RW) || \
378 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
379 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
380 ((TYPE) == MPU_REGION_PRIV_RO) || \
381 ((TYPE) == MPU_REGION_PRIV_RO_URO))
Dstm32h7xx_hal_fdcan.h2279 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ argument
2280 ((TYPE) == FDCAN_FILTER_DUAL ) || \
2281 ((TYPE) == FDCAN_FILTER_MASK ))
2282 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ argument
2283 ((TYPE) == FDCAN_FILTER_DUAL ) || \
2284 ((TYPE) == FDCAN_FILTER_MASK ) || \
2285 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
2286 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ argument
2287 ((TYPE) == FDCAN_REMOTE_FRAME))
2360 #define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \ argument
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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_mmc.h372 #define IS_MMC_ERASE_TYPE(TYPE) (((TYPE) == HAL_MMC_ERASE) || \ argument
373 ((TYPE) == HAL_MMC_TRIM) || \
374 ((TYPE) == HAL_MMC_DISCARD) || \
375 ((TYPE) == HAL_MMC_SECURE_ERASE) || \
376 ((TYPE) == HAL_MMC_SECURE_TRIM_STEP1) || \
377 ((TYPE) == HAL_MMC_SECURE_TRIM_STEP2))
391 #define IS_MMC_SRT_TYPE(TYPE) (((TYPE) == HAL_MMC_SRT_ERASE) || \ argument
392 ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_ERASE) || \
393 ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM) || \
394 ((TYPE) == HAL_MMC_SRT_VENDOR_DEFINED))

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