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Searched refs:TIM_CCR1_CCR1_Pos (Results 1 – 25 of 254) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wb0x/soc/
Dstm32wb05.h5327 #define TIM_CCR1_CCR1_Pos (0UL) /*!<TIM CCR1: C… macro
5330 …fine TIM_CCR1_CCR1_0 (0x1U << TIM_CCR1_CCR1_Pos)
5331 …fine TIM_CCR1_CCR1_1 (0x2U << TIM_CCR1_CCR1_Pos)
5332 …fine TIM_CCR1_CCR1_2 (0x4U << TIM_CCR1_CCR1_Pos)
5333 …fine TIM_CCR1_CCR1_3 (0x8U << TIM_CCR1_CCR1_Pos)
5334 …ine TIM_CCR1_CCR1_4 (0x10U << TIM_CCR1_CCR1_Pos)
5335 …ine TIM_CCR1_CCR1_5 (0x20U << TIM_CCR1_CCR1_Pos)
5336 …ine TIM_CCR1_CCR1_6 (0x40U << TIM_CCR1_CCR1_Pos)
5337 …ine TIM_CCR1_CCR1_7 (0x80U << TIM_CCR1_CCR1_Pos)
5338 …ne TIM_CCR1_CCR1_8 (0x100U << TIM_CCR1_CCR1_Pos)
[all …]
Dstm32wb07.h5860 #define TIM_CCR1_CCR1_Pos (0UL) /*!<TIM CCR1: C… macro
5863 …fine TIM_CCR1_CCR1_0 (0x1U << TIM_CCR1_CCR1_Pos)
5864 …fine TIM_CCR1_CCR1_1 (0x2U << TIM_CCR1_CCR1_Pos)
5865 …fine TIM_CCR1_CCR1_2 (0x4U << TIM_CCR1_CCR1_Pos)
5866 …fine TIM_CCR1_CCR1_3 (0x8U << TIM_CCR1_CCR1_Pos)
5867 …ine TIM_CCR1_CCR1_4 (0x10U << TIM_CCR1_CCR1_Pos)
5868 …ine TIM_CCR1_CCR1_5 (0x20U << TIM_CCR1_CCR1_Pos)
5869 …ine TIM_CCR1_CCR1_6 (0x40U << TIM_CCR1_CCR1_Pos)
5870 …ine TIM_CCR1_CCR1_7 (0x80U << TIM_CCR1_CCR1_Pos)
5871 …ne TIM_CCR1_CCR1_8 (0x100U << TIM_CCR1_CCR1_Pos)
[all …]
Dstm32wb09.h5847 #define TIM_CCR1_CCR1_Pos (0UL) /*!<TIM CCR1: C… macro
5850 …fine TIM_CCR1_CCR1_0 (0x1U << TIM_CCR1_CCR1_Pos)
5851 …fine TIM_CCR1_CCR1_1 (0x2U << TIM_CCR1_CCR1_Pos)
5852 …fine TIM_CCR1_CCR1_2 (0x4U << TIM_CCR1_CCR1_Pos)
5853 …fine TIM_CCR1_CCR1_3 (0x8U << TIM_CCR1_CCR1_Pos)
5854 …ine TIM_CCR1_CCR1_4 (0x10U << TIM_CCR1_CCR1_Pos)
5855 …ine TIM_CCR1_CCR1_5 (0x20U << TIM_CCR1_CCR1_Pos)
5856 …ine TIM_CCR1_CCR1_6 (0x40U << TIM_CCR1_CCR1_Pos)
5857 …ine TIM_CCR1_CCR1_7 (0x80U << TIM_CCR1_CCR1_Pos)
5858 …ne TIM_CCR1_CCR1_8 (0x100U << TIM_CCR1_CCR1_Pos)
[all …]
Dstm32wb06.h5860 #define TIM_CCR1_CCR1_Pos (0UL) /*!<TIM CCR1: C… macro
5863 …fine TIM_CCR1_CCR1_0 (0x1U << TIM_CCR1_CCR1_Pos)
5864 …fine TIM_CCR1_CCR1_1 (0x2U << TIM_CCR1_CCR1_Pos)
5865 …fine TIM_CCR1_CCR1_2 (0x4U << TIM_CCR1_CCR1_Pos)
5866 …fine TIM_CCR1_CCR1_3 (0x8U << TIM_CCR1_CCR1_Pos)
5867 …ine TIM_CCR1_CCR1_4 (0x10U << TIM_CCR1_CCR1_Pos)
5868 …ine TIM_CCR1_CCR1_5 (0x20U << TIM_CCR1_CCR1_Pos)
5869 …ine TIM_CCR1_CCR1_6 (0x40U << TIM_CCR1_CCR1_Pos)
5870 …ine TIM_CCR1_CCR1_7 (0x80U << TIM_CCR1_CCR1_Pos)
5871 …ne TIM_CCR1_CCR1_8 (0x100U << TIM_CCR1_CCR1_Pos)
[all …]
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h4038 #define TIM_CCR1_CCR1_Pos (0U) macro
4039 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32f101xb.h4100 #define TIM_CCR1_CCR1_Pos (0U) macro
4101 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32f100xb.h4505 #define TIM_CCR1_CCR1_Pos (0U) macro
4506 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32f102x6.h4087 #define TIM_CCR1_CCR1_Pos (0U) macro
4088 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h4630 #define TIM_CCR1_CCR1_Pos (0U) macro
4631 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32f030x8.h4665 #define TIM_CCR1_CCR1_Pos (0U) macro
4666 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32f070x6.h4713 #define TIM_CCR1_CCR1_Pos (0U) macro
4714 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32f031x6.h4832 #define TIM_CCR1_CCR1_Pos (0U) macro
4833 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32f030xc.h4998 #define TIM_CCR1_CCR1_Pos (0U) macro
4999 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32f038xx.h4801 #define TIM_CCR1_CCR1_Pos (0U) macro
4802 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32f070xb.h4865 #define TIM_CCR1_CCR1_Pos (0U) macro
4866 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h5438 #define TIM_CCR1_CCR1_Pos (0U) macro
5439 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32l010x8.h5096 #define TIM_CCR1_CCR1_Pos (0U) macro
5097 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32l010xb.h5144 #define TIM_CCR1_CCR1_Pos (0U) macro
5145 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32l011xx.h5178 #define TIM_CCR1_CCR1_Pos (0U) macro
5179 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32l021xx.h5315 #define TIM_CCR1_CCR1_Pos (0U) macro
5316 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32l031xx.h5301 #define TIM_CCR1_CCR1_Pos (0U) macro
5302 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32l051xx.h5455 #define TIM_CCR1_CCR1_Pos (0U) macro
5456 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32l010x4.h5051 #define TIM_CCR1_CCR1_Pos (0U) macro
5052 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32l010x6.h5103 #define TIM_CCR1_CCR1_Pos (0U) macro
5104 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Dstm32l081xx.h5769 #define TIM_CCR1_CCR1_Pos (0U) macro
5770 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */

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