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Searched refs:TIM1_OR1_ETR_ADC1_RMP_Pos (Results 1 – 25 of 27) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h8717 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
8718 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
8720 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
8721 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l412xx.h8492 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
8493 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
8495 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
8496 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l433xx.h13198 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
13199 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
13201 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
13202 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l451xx.h13303 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
13304 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
13306 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
13307 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l442xx.h12364 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
12365 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
12367 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
12368 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l431xx.h12969 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
12970 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
12972 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
12973 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l432xx.h12139 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
12140 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
12142 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
12143 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l443xx.h13423 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
13424 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
13426 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
13427 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l471xx.h14315 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
14316 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
14318 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
14319 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l452xx.h13381 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
13382 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
13384 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
13385 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l462xx.h13606 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
13607 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
13609 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
13610 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l475xx.h14479 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
14480 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
14482 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
14483 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l476xx.h14636 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
14637 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
14639 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
14640 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l486xx.h14855 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
14856 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
14858 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
14859 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l485xx.h14704 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
14705 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
14707 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
14708 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4a6xx.h16186 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
16187 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
16189 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
16190 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l496xx.h15846 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
15847 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
15849 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
15850 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4r5xx.h16326 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
16327 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
16329 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
16330 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4r7xx.h16825 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
16826 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
16828 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
16829 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4s5xx.h16673 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
16674 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
16676 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
16677 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4s7xx.h17172 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
17173 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
17175 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
17176 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4p5xx.h17326 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
17327 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
17329 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
17330 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4q5xx.h17837 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
17838 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
17840 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
17841 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h14840 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
14841 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
14843 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
14844 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32l562xx.h15579 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) macro
15580 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
15582 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
15583 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */

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