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Searched refs:TIM16_OR1_TI1_RMP_Pos (Results 1 – 25 of 32) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h8824 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
8825 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
8827 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
8828 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
8829 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l412xx.h8599 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
8600 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
8602 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
8603 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
8604 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l433xx.h13311 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
13312 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
13314 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
13315 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
13316 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l442xx.h12477 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
12478 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
12480 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
12481 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
12482 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l431xx.h13082 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
13083 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
13085 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
13086 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
13087 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l432xx.h12252 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
12253 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
12255 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
12256 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
12257 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l443xx.h13536 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
13537 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
13539 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
13540 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
13541 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l451xx.h13439 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
13440 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
13442 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
13443 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4a6xx.h16397 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
16398 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
16400 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
16401 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
16402 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l496xx.h16057 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
16058 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
16060 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
16061 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
16062 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l471xx.h14526 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
14527 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14529 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14530 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l452xx.h13517 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
13518 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
13520 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
13521 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l462xx.h13742 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
13743 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
13745 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
13746 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4p5xx.h17526 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
17527 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
17529 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
17530 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
17531 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l4q5xx.h18037 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
18038 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
18040 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
18041 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
18042 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Dstm32l475xx.h14690 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
14691 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14693 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14694 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l476xx.h14847 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
14848 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14850 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14851 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l486xx.h15066 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
15067 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
15069 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
15070 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l485xx.h14915 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
14916 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14918 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14919 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h9348 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
9349 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
9351 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
9352 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32wle5xx.h9348 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
9349 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
9351 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
9352 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32wl5mxx.h11020 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
11021 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
11023 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
11024 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32wl54xx.h11020 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
11021 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
11023 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
11024 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32wl55xx.h11020 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
11021 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
11023 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
11024 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h15033 #define TIM16_OR1_TI1_RMP_Pos (0U) macro
15034 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
15036 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
15037 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */

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