Home
last modified time | relevance | path

Searched refs:SRAM2_BASE_S (Results 1 – 25 of 27) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_gtzc.c725 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()
870 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_GetConfigMemAttributes()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_gtzc.c870 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()
965 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_GetConfigMemAttributes()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_gtzc.c1075 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()
1220 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_GetConfigMemAttributes()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_gtzc.c1143 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()
1324 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_GetConfigMemAttributes()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba52xx.h1101 #define SRAM2_BASE_S 0x30010000UL /*!< SRAM2 secure base address … macro
1378 #define SRAM2_BASE SRAM2_BASE_S
Dstm32wba54xx.h1170 #define SRAM2_BASE_S 0x30010000UL /*!< SRAM2 secure base address … macro
1468 #define SRAM2_BASE SRAM2_BASE_S
Dstm32wba5mxx.h1170 #define SRAM2_BASE_S 0x30010000UL /*!< SRAM2 secure base address … macro
1468 #define SRAM2_BASE SRAM2_BASE_S
Dstm32wba55xx.h1170 #define SRAM2_BASE_S 0x30010000UL /*!< SRAM2 secure base address … macro
1468 #define SRAM2_BASE SRAM2_BASE_S
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h1513 #define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2(64 KB) base address */ macro
2076 #define SRAM2_BASE SRAM2_BASE_S
Dstm32l562xx.h1594 #define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2(64 KB) base address */ macro
2178 #define SRAM2_BASE SRAM2_BASE_S
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h1639 #define SRAM2_BASE_S (0x30020000UL) /*!< SRAM2 (80 KB) secure base address */ macro
2250 #define SRAM2_BASE SRAM2_BASE_S
Dstm32h562xx.h1753 #define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2437 #define SRAM2_BASE SRAM2_BASE_S
Dstm32h533xx.h1710 #define SRAM2_BASE_S (0x30020000UL) /*!< SRAM2 (80 KB) secure base address */ macro
2366 #define SRAM2_BASE SRAM2_BASE_S
Dstm32h573xx.h2007 #define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2751 #define SRAM2_BASE SRAM2_BASE_S
Dstm32h563xx.h1936 #define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2635 #define SRAM2_BASE SRAM2_BASE_S
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h1676 #define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2208 #define SRAM2_BASE SRAM2_BASE_S
Dstm32u535xx.h1589 #define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2096 #define SRAM2_BASE SRAM2_BASE_S
Dstm32u575xx.h1825 #define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2404 #define SRAM2_BASE SRAM2_BASE_S
Dstm32u585xx.h1918 #define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2537 #define SRAM2_BASE SRAM2_BASE_S
Dstm32u595xx.h1885 #define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2489 #define SRAM2_BASE SRAM2_BASE_S
Dstm32u5a5xx.h1978 #define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2622 #define SRAM2_BASE SRAM2_BASE_S
Dstm32u5f7xx.h2065 #define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2704 #define SRAM2_BASE SRAM2_BASE_S
Dstm32u599xx.h2081 #define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2716 #define SRAM2_BASE SRAM2_BASE_S
Dstm32u5g7xx.h2158 #define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2837 #define SRAM2_BASE SRAM2_BASE_S
Dstm32u5f9xx.h2172 #define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ macro
2820 #define SRAM2_BASE SRAM2_BASE_S

12