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Searched refs:SPI_RXFIFO_THRESHOLD (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_spi.c1074 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1079 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1339 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1344 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1495 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1733 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1739 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1874 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1879 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2098 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_hal_spi.c1067 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1072 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1330 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1335 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1486 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1720 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1726 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1858 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1863 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2074 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_spi.c1075 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1080 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1340 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1345 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1496 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1734 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1740 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1875 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1880 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2099 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/src/
Dstm32wb0x_hal_spi.c1074 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1079 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1339 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1344 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1495 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1733 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1739 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1874 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1879 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2098 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_hal_spi.c1069 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1074 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1329 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1334 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1457 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1683 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1689 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1824 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1829 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2048 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_hal_spi.c1074 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1079 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1339 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1344 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1495 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1733 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1739 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1874 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1879 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2098 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_hal_spi.c1074 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1079 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1339 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1344 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1495 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1733 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1739 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1874 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1879 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2107 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_spi.c1069 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1074 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1333 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1338 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1489 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1723 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1729 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1862 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1867 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2078 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_spi.c1069 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1074 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1333 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1338 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1489 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1723 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1729 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1862 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1867 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2078 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_hal_spi.c1054 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1059 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1317 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1322 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1679 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1685 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1820 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1825 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2053 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
2058 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_hal_spi.c1054 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1059 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1317 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1322 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1679 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1685 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1820 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1825 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2044 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
2049 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_hal_spi.c1054 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1059 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive()
1317 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1322 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive()
1679 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1685 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_IT()
1820 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
1825 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_TransmitReceive_IT()
2044 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
2049 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); in HAL_SPI_Receive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_spi.h356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH macro