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Searched refs:SPI_DR_DR_Pos (Results 1 – 25 of 201) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wb0x/soc/
Dstm32wb05.h2549 #define SPI_DR_DR_Pos (0UL) /*!<SPI DR: DR … macro
2552 #define SPI_DR_DR_0 (0x1U << SPI_DR_DR_Pos)
2553 #define SPI_DR_DR_1 (0x2U << SPI_DR_DR_Pos)
2554 #define SPI_DR_DR_2 (0x4U << SPI_DR_DR_Pos)
2555 #define SPI_DR_DR_3 (0x8U << SPI_DR_DR_Pos)
2556 #define SPI_DR_DR_4 (0x10U << SPI_DR_DR_Pos)
2557 #define SPI_DR_DR_5 (0x20U << SPI_DR_DR_Pos)
2558 #define SPI_DR_DR_6 (0x40U << SPI_DR_DR_Pos)
2559 #define SPI_DR_DR_7 (0x80U << SPI_DR_DR_Pos)
2560 #define SPI_DR_DR_8 (0x100U << SPI_DR_DR_Pos)
[all …]
Dstm32wb07.h2643 #define SPI_DR_DR_Pos (0UL) /*!<SPI DR: DR … macro
2646 #define SPI_DR_DR_0 (0x1U << SPI_DR_DR_Pos)
2647 #define SPI_DR_DR_1 (0x2U << SPI_DR_DR_Pos)
2648 #define SPI_DR_DR_2 (0x4U << SPI_DR_DR_Pos)
2649 #define SPI_DR_DR_3 (0x8U << SPI_DR_DR_Pos)
2650 #define SPI_DR_DR_4 (0x10U << SPI_DR_DR_Pos)
2651 #define SPI_DR_DR_5 (0x20U << SPI_DR_DR_Pos)
2652 #define SPI_DR_DR_6 (0x40U << SPI_DR_DR_Pos)
2653 #define SPI_DR_DR_7 (0x80U << SPI_DR_DR_Pos)
2654 #define SPI_DR_DR_8 (0x100U << SPI_DR_DR_Pos)
[all …]
Dstm32wb09.h2574 #define SPI_DR_DR_Pos (0UL) /*!<SPI DR: DR … macro
2577 #define SPI_DR_DR_0 (0x1U << SPI_DR_DR_Pos)
2578 #define SPI_DR_DR_1 (0x2U << SPI_DR_DR_Pos)
2579 #define SPI_DR_DR_2 (0x4U << SPI_DR_DR_Pos)
2580 #define SPI_DR_DR_3 (0x8U << SPI_DR_DR_Pos)
2581 #define SPI_DR_DR_4 (0x10U << SPI_DR_DR_Pos)
2582 #define SPI_DR_DR_5 (0x20U << SPI_DR_DR_Pos)
2583 #define SPI_DR_DR_6 (0x40U << SPI_DR_DR_Pos)
2584 #define SPI_DR_DR_7 (0x80U << SPI_DR_DR_Pos)
2585 #define SPI_DR_DR_8 (0x100U << SPI_DR_DR_Pos)
[all …]
Dstm32wb06.h2643 #define SPI_DR_DR_Pos (0UL) /*!<SPI DR: DR … macro
2646 #define SPI_DR_DR_0 (0x1U << SPI_DR_DR_Pos)
2647 #define SPI_DR_DR_1 (0x2U << SPI_DR_DR_Pos)
2648 #define SPI_DR_DR_2 (0x4U << SPI_DR_DR_Pos)
2649 #define SPI_DR_DR_3 (0x8U << SPI_DR_DR_Pos)
2650 #define SPI_DR_DR_4 (0x10U << SPI_DR_DR_Pos)
2651 #define SPI_DR_DR_5 (0x20U << SPI_DR_DR_Pos)
2652 #define SPI_DR_DR_6 (0x40U << SPI_DR_DR_Pos)
2653 #define SPI_DR_DR_7 (0x80U << SPI_DR_DR_Pos)
2654 #define SPI_DR_DR_8 (0x100U << SPI_DR_DR_Pos)
[all …]
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h4403 #define SPI_DR_DR_Pos (0U) macro
4404 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32f101xb.h4465 #define SPI_DR_DR_Pos (0U) macro
4466 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32f100xb.h4870 #define SPI_DR_DR_Pos (0U) macro
4871 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32f102x6.h5522 #define SPI_DR_DR_Pos (0U) macro
5523 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h3878 #define SPI_DR_DR_Pos (0U) macro
3879 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
Dstm32f030x8.h3922 #define SPI_DR_DR_Pos (0U) macro
3923 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
Dstm32f070x6.h3958 #define SPI_DR_DR_Pos (0U) macro
3959 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
Dstm32f031x6.h4039 #define SPI_DR_DR_Pos (0U) macro
4040 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
Dstm32f030xc.h4248 #define SPI_DR_DR_Pos (0U) macro
4249 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
Dstm32f038xx.h4011 #define SPI_DR_DR_Pos (0U) macro
4012 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
Dstm32f070xb.h4116 #define SPI_DR_DR_Pos (0U) macro
4117 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h4774 #define SPI_DR_DR_Pos (0U) macro
4775 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32l010x8.h4449 #define SPI_DR_DR_Pos (0U) macro
4450 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32l010xb.h4497 #define SPI_DR_DR_Pos (0U) macro
4498 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32l011xx.h4514 #define SPI_DR_DR_Pos (0U) macro
4515 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32l021xx.h4651 #define SPI_DR_DR_Pos (0U) macro
4652 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32l031xx.h4637 #define SPI_DR_DR_Pos (0U) macro
4638 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32l051xx.h4746 #define SPI_DR_DR_Pos (0U) macro
4747 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32l010x4.h4405 #define SPI_DR_DR_Pos (0U) macro
4406 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32l010x6.h4457 #define SPI_DR_DR_Pos (0U) macro
4458 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Dstm32l081xx.h5017 #define SPI_DR_DR_Pos (0U) macro
5018 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */

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