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Searched refs:SDTR (Results 1 – 25 of 61) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c868 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
880 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
886 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], in FMC_SDRAM_Timing_Init()
911 Device->SDTR[Bank] = 0x0FFFFFFFU; in FMC_SDRAM_DeInit()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_fmc.c868 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
880 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
886 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], in FMC_SDRAM_Timing_Init()
911 Device->SDTR[Bank] = 0x0FFFFFFFU; in FMC_SDRAM_DeInit()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_fmc.c882 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
894 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
900 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], in FMC_SDRAM_Timing_Init()
925 Device->SDTR[Bank] = 0x0FFFFFFFU; in FMC_SDRAM_DeInit()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_fmc.c938 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
950 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
956 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], in FMC_SDRAM_Timing_Init()
981 Device->SDTR[Bank] = 0x0FFFFFFFU; in FMC_SDRAM_DeInit()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fmc.c1260 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
1272 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
1278 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], in FMC_SDRAM_Timing_Init()
1303 Device->SDTR[Bank] = 0x0FFFFFFFU; in FMC_SDRAM_DeInit()
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dsystem_stm32f4xx.c371 FMC_Bank5_6->SDTR[0] = 0x01115351; in SystemInit_ExtMemCtl()
579 FMC_Bank5_6->SDTR[0] = 0x01115351; in SystemInit_ExtMemCtl()
Dstm32f427xx.h562 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f446xx.h448 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f429xx.h564 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f439xx.h565 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f437xx.h563 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f469xx.h627 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_fmc.c859 MODIFY_REG(Device->SDTR, in FMC_SDRAM_Timing_Init()
885 Device->SDTR = 0x0FFFFFFFU; in FMC_SDRAM_DeInit()
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h419 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f722xx.h419 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f730xx.h420 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f733xx.h420 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f732xx.h420 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f750xx.h569 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f745xx.h566 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f756xx.h569 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f746xx.h568 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f765xx.h610 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f777xx.h614 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member
Dstm32f767xx.h613 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ member

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