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Searched refs:SDCMR (Results 1 – 25 of 61) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dsystem_stm32f4xx.c375 FMC_Bank5_6->SDCMR = 0x00000011; in SystemInit_ExtMemCtl()
386 FMC_Bank5_6->SDCMR = 0x00000012; in SystemInit_ExtMemCtl()
395 FMC_Bank5_6->SDCMR = 0x00000073; in SystemInit_ExtMemCtl()
404 FMC_Bank5_6->SDCMR = 0x00046014; in SystemInit_ExtMemCtl()
583 FMC_Bank5_6->SDCMR = 0x00000011; in SystemInit_ExtMemCtl()
594 FMC_Bank5_6->SDCMR = 0x00000012; in SystemInit_ExtMemCtl()
604 FMC_Bank5_6->SDCMR = 0x000000F3; in SystemInit_ExtMemCtl()
606 FMC_Bank5_6->SDCMR = 0x00000073; in SystemInit_ExtMemCtl()
617 FMC_Bank5_6->SDCMR = 0x00044014; in SystemInit_ExtMemCtl()
619 FMC_Bank5_6->SDCMR = 0x00046014; in SystemInit_ExtMemCtl()
Dstm32f427xx.h563 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f446xx.h449 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f429xx.h565 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f439xx.h566 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f437xx.h564 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f469xx.h628 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c912 Device->SDCMR = 0x00000000U; in FMC_SDRAM_DeInit()
992 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC… in FMC_SDRAM_SendCommand()
1033 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); in FMC_SDRAM_SetAutoRefreshNumber()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_fmc.c886 Device->SDCMR = 0x00000000U; in FMC_SDRAM_DeInit()
966 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_DS2 | FMC_SDCMR_DS1 | FMC_SDCMR_NRFS | FMC_S… in FMC_SDRAM_SendCommand()
1007 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); in FMC_SDRAM_SetAutoRefreshNumber()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_fmc.c912 Device->SDCMR = 0x00000000U; in FMC_SDRAM_DeInit()
992 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC… in FMC_SDRAM_SendCommand()
1033 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); in FMC_SDRAM_SetAutoRefreshNumber()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_fmc.c926 Device->SDCMR = 0x00000000U; in FMC_SDRAM_DeInit()
1006 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC… in FMC_SDRAM_SendCommand()
1047 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); in FMC_SDRAM_SetAutoRefreshNumber()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_fmc.c982 Device->SDCMR = 0x00000000U; in FMC_SDRAM_DeInit()
1062 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC… in FMC_SDRAM_SendCommand()
1103 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); in FMC_SDRAM_SetAutoRefreshNumber()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fmc.c1304 Device->SDCMR = 0x00000000U; in FMC_SDRAM_DeInit()
1385 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC… in FMC_SDRAM_SendCommand()
1439 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); in FMC_SDRAM_SetAutoRefreshNumber()
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h420 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f722xx.h420 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f730xx.h421 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f733xx.h421 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f732xx.h421 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f750xx.h570 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f745xx.h567 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f756xx.h570 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f746xx.h569 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f765xx.h611 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f777xx.h615 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member
Dstm32f767xx.h614 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ member

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