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Searched refs:RCC_PLL1DIVR_PLL1R_Pos (Results 1 – 25 of 38) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_rcc.c819 ((RCC_OscInitStruct->PLL1.PLLR - 1u) << RCC_PLL1DIVR_PLL1R_Pos)); in HAL_RCC_OscConfig()
888 …(((tmpreg2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) != (RCC_OscInitStruct->PLL1.PLLR - 1u)… in HAL_RCC_OscConfig()
1425 pllr = ((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U; in HAL_RCC_GetPLL1RFreq()
1506 RCC_OscInitStruct->PLL1.PLLR = (((regvalue & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h2311 …L1DIVR_PLL1R, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << RCC_PLL1DIVR_PLL1R_Pos)); in LL_RCC_PLL1_ConfigDomain_PLL1R()
2461 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); in LL_RCC_PLL1_SetR()
2472 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); in LL_RCC_PLL1_GetR()
Dstm32wbaxx_hal_rcc.h2028 …(((__PLL1R__) - 1U) << RCC_PLL1DIVR_PLL1R_Pos))); …
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc.c1283 RCC_PLL1DIVR_PLL1R_Pos) != (pRCC_OscInitStruct->PLL.PLLR - 1U))) in HAL_RCC_OscConfig()
1797 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); in HAL_RCC_GetSysClockFreq()
1944 …InitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dsystem_stm32u5xx.c335 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); in SystemCoreClockUpdate()
Dsystem_stm32u5xx_s.c358 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); in SystemCoreClockUpdate()
Dstm32u545xx.h14605 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
14606 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
14608 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
14609 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
14610 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
14611 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
14612 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
14613 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
14614 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32u535xx.h14092 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
14093 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
14095 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
14096 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
14097 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
14098 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
14099 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
14100 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
14101 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32u575xx.h15500 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
15501 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
15503 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
15504 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
15505 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
15506 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
15507 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
15508 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
15509 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dsystem_stm32wbaxx.c320 pllr = ((tmp2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U; in SystemCoreClockUpdate()
Dsystem_stm32wbaxx_s.c342 pllr = ((tmp2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U; in SystemCoreClockUpdate()
Dstm32wba50xx.h6061 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
6062 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
6064 #define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
6065 #define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
6066 #define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
6067 #define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
6068 #define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
6069 #define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
6070 #define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32wba52xx.h9835 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
9836 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
9838 #define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
9839 #define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
9840 #define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
9841 #define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
9842 #define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
9843 #define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
9844 #define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32wba54xx.h10107 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
10108 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
10110 #define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
10111 #define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
10112 #define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
10113 #define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
10114 #define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
10115 #define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
10116 #define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32wba5mxx.h10125 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
10126 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
10128 #define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
10129 #define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
10130 #define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
10131 #define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
10132 #define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
10133 #define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
10134 #define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32wba55xx.h10125 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
10126 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
10128 #define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
10129 #define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
10130 #define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
10131 #define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
10132 #define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
10133 #define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
10134 #define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc.c962 RCC_PLL1DIVR_PLL1R_Pos) != (pOscInitStruct->PLL.PLLR - 1U))) in HAL_RCC_OscConfig()
1608 …pOscInitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) +… in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h3896 RCC_PLL1DIVR_PLL1R_Pos)); in LL_RCC_PLL1_ConfigDomain_SYS()
4065 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); in LL_RCC_PLL1_SetR()
4077 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); in LL_RCC_PLL1_GetR()
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h8589 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
8590 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
8592 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
8593 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
8594 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
8595 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
8596 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
8597 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
8598 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32h523xx.h12765 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
12766 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
12768 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
12769 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
12770 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
12771 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
12772 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
12773 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
12774 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32h562xx.h13445 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
13446 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
13448 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
13449 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
13450 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
13451 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
13452 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
13453 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
13454 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32h533xx.h13284 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
13285 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
13287 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
13288 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
13289 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
13290 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
13291 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
13292 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
13293 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32h573xx.h16048 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
16049 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
16051 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
16052 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
16053 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
16054 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
16055 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
16056 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
16057 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
Dstm32h563xx.h15529 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro
15530 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000…
15532 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000…
15533 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000…
15534 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000…
15535 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000…
15536 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000…
15537 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000…
15538 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000…
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h4436 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); in LL_RCC_PLL1_SetR()
4447 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); in LL_RCC_PLL1_GetR()

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