Searched refs:RCC_PLL1DIVR1_DIVN_Pos (Results 1 – 5 of 5) sorted by relevance
3767 ((P - 1UL) << RCC_PLL1DIVR1_DIVP_Pos) | ((N - 1UL) << RCC_PLL1DIVR1_DIVN_Pos)); in LL_RCC_PLL1_ConfigDomain_SYS()3991 …return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVN) >> RCC_PLL1DIVR1_DIVN_Pos) + 1UL); in LL_RCC_PLL1_GetN()4062 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVN, (N - 1UL) << RCC_PLL1DIVR1_DIVN_Pos); in LL_RCC_PLL1_SetN()
14854 #define RCC_PLL1DIVR1_DIVN_Pos (0U) macro14855 #define RCC_PLL1DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x000001FF */14857 #define RCC_PLL1DIVR1_DIVN_0 (0x001UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000001 */14858 #define RCC_PLL1DIVR1_DIVN_1 (0x002UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000002 */14859 #define RCC_PLL1DIVR1_DIVN_2 (0x004UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000004 */14860 #define RCC_PLL1DIVR1_DIVN_3 (0x008UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000008 */14861 #define RCC_PLL1DIVR1_DIVN_4 (0x010UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000010 */14862 #define RCC_PLL1DIVR1_DIVN_5 (0x020UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000020 */14863 #define RCC_PLL1DIVR1_DIVN_6 (0x040UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000040 */14864 #define RCC_PLL1DIVR1_DIVN_7 (0x080UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000080 */[all …]
15888 #define RCC_PLL1DIVR1_DIVN_Pos (0U) macro15889 #define RCC_PLL1DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x000001FF */15891 #define RCC_PLL1DIVR1_DIVN_0 (0x001UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000001 */15892 #define RCC_PLL1DIVR1_DIVN_1 (0x002UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000002 */15893 #define RCC_PLL1DIVR1_DIVN_2 (0x004UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000004 */15894 #define RCC_PLL1DIVR1_DIVN_3 (0x008UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000008 */15895 #define RCC_PLL1DIVR1_DIVN_4 (0x010UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000010 */15896 #define RCC_PLL1DIVR1_DIVN_5 (0x020UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000020 */15897 #define RCC_PLL1DIVR1_DIVN_6 (0x040UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000040 */15898 #define RCC_PLL1DIVR1_DIVN_7 (0x080UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000080 */[all …]
15486 #define RCC_PLL1DIVR1_DIVN_Pos (0U) macro15487 #define RCC_PLL1DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x000001FF */15489 #define RCC_PLL1DIVR1_DIVN_0 (0x001UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000001 */15490 #define RCC_PLL1DIVR1_DIVN_1 (0x002UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000002 */15491 #define RCC_PLL1DIVR1_DIVN_2 (0x004UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000004 */15492 #define RCC_PLL1DIVR1_DIVN_3 (0x008UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000008 */15493 #define RCC_PLL1DIVR1_DIVN_4 (0x010UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000010 */15494 #define RCC_PLL1DIVR1_DIVN_5 (0x020UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000020 */15495 #define RCC_PLL1DIVR1_DIVN_6 (0x040UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000040 */15496 #define RCC_PLL1DIVR1_DIVN_7 (0x080UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000080 */[all …]
15254 #define RCC_PLL1DIVR1_DIVN_Pos (0U) macro15255 #define RCC_PLL1DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x000001FF */15257 #define RCC_PLL1DIVR1_DIVN_0 (0x001UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000001 */15258 #define RCC_PLL1DIVR1_DIVN_1 (0x002UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000002 */15259 #define RCC_PLL1DIVR1_DIVN_2 (0x004UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000004 */15260 #define RCC_PLL1DIVR1_DIVN_3 (0x008UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000008 */15261 #define RCC_PLL1DIVR1_DIVN_4 (0x010UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000010 */15262 #define RCC_PLL1DIVR1_DIVN_5 (0x020UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000020 */15263 #define RCC_PLL1DIVR1_DIVN_6 (0x040UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000040 */15264 #define RCC_PLL1DIVR1_DIVN_7 (0x080UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000080 */[all …]
