Lines Matching refs:RCC_PLL1DIVR1_DIVN_Pos

14854 #define RCC_PLL1DIVR1_DIVN_Pos        (0U)  macro
14855 #define RCC_PLL1DIVR1_DIVN_Msk        (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x000001FF */
14857 #define RCC_PLL1DIVR1_DIVN_0          (0x001UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000001 */
14858 #define RCC_PLL1DIVR1_DIVN_1          (0x002UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000002 */
14859 #define RCC_PLL1DIVR1_DIVN_2          (0x004UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000004 */
14860 #define RCC_PLL1DIVR1_DIVN_3          (0x008UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000008 */
14861 #define RCC_PLL1DIVR1_DIVN_4          (0x010UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000010 */
14862 #define RCC_PLL1DIVR1_DIVN_5          (0x020UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000020 */
14863 #define RCC_PLL1DIVR1_DIVN_6          (0x040UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000040 */
14864 #define RCC_PLL1DIVR1_DIVN_7          (0x080UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000080 */
14865 #define RCC_PLL1DIVR1_DIVN_8          (0x100UL << RCC_PLL1DIVR1_DIVN_Pos)    /*!< 0x00000100 */