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Searched refs:RCC_PLL1CFGR_PLL1M_Pos (Results 1 – 25 of 40) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_rcc.c812 … ((RCC_OscInitStruct->PLL1.PLLM - 1u) << RCC_PLL1CFGR_PLL1M_Pos) | RCC_PLL1CFGR_PLL1REN); in HAL_RCC_OscConfig()
884 …(((tmpreg1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) != (RCC_OscInitStruct->PLL1.PLLM - 1u)… in HAL_RCC_OscConfig()
1489 RCC_OscInitStruct->PLL1.PLLM = (((regvalue & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U); in HAL_RCC_GetOscConfig()
1776 tmp = ((tmpreg1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in RCC_PLL1_GetVCOOutputFreq()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h2310 …FGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); in LL_RCC_PLL1_ConfigDomain_PLL1R()
2333 …FGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); in LL_RCC_PLL1_ConfigDomain_PLL1P()
2356 …FGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); in LL_RCC_PLL1_ConfigDomain_PLL1Q()
2482 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos); in LL_RCC_PLL1_SetDivider()
2492 return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL); in LL_RCC_PLL1_GetDivider()
Dstm32wbaxx_hal_rcc.h2026 … | RCC_PLL1CFGR_PLL1M), ((__PLL1SOURCE__) | (((__PLL1M__) - 1U) << RCC_PLL1CFGR_PLL1M_Pos))); \
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc.c955 RCC_PLL1CFGR_PLL1M_Pos) != (pOscInitStruct->PLL.PLLM)) || in HAL_RCC_OscConfig()
1432 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); in HAL_RCC_GetSysClockFreq()
1605 pOscInitStruct->PLL.PLLM = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h3893 ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); in LL_RCC_PLL1_ConfigDomain_SYS()
3921 ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); in LL_RCC_PLL1_ConfigDomain_SAI()
3949 ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); in LL_RCC_PLL1_ConfigDomain_48M()
4088 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos); in LL_RCC_PLL1_SetDivider()
4099 return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL); in LL_RCC_PLL1_GetDivider()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc.c1275 RCC_PLL1CFGR_PLL1M_Pos) != (pRCC_OscInitStruct->PLL.PLLM - 1U)) || in HAL_RCC_OscConfig()
1773 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in HAL_RCC_GetSysClockFreq()
1941 …InitStruct->PLL.PLLM = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dsystem_stm32u5xx.c311 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
Dsystem_stm32u5xx_s.c334 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dsystem_stm32wbaxx.c318 pllm = ((tmp1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
Dsystem_stm32wbaxx_s.c340 pllm = ((tmp1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
Dstm32wba50xx.h6003 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
6004 #define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700…
6006 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
6007 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
6008 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
Dstm32wba52xx.h9777 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
9778 #define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700…
9780 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
9781 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
9782 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
Dstm32wba54xx.h10049 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
10050 #define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700…
10052 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
10053 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
10054 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
Dstm32wba5mxx.h10067 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
10068 #define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700…
10070 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
10071 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
10072 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
Dstm32wba55xx.h10067 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
10068 #define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700…
10070 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
10071 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
10072 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dsystem_stm32h5xx.c346 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); in SystemCoreClockUpdate()
Dsystem_stm32h5xx_s.c360 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); in SystemCoreClockUpdate()
Dstm32h503xx.h8501 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
8502 #define RCC_PLL1CFGR_PLL1M_Msk (0x3FUL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00003F00…
8504 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
8505 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
8506 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
8507 #define RCC_PLL1CFGR_PLL1M_3 (0x08UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000800…
8508 #define RCC_PLL1CFGR_PLL1M_4 (0x10UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00001000…
8509 #define RCC_PLL1CFGR_PLL1M_5 (0x20UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00002000…
Dstm32h523xx.h12641 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
12642 #define RCC_PLL1CFGR_PLL1M_Msk (0x3FUL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00003F00…
12644 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
12645 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
12646 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
12647 #define RCC_PLL1CFGR_PLL1M_3 (0x08UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000800…
12648 #define RCC_PLL1CFGR_PLL1M_4 (0x10UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00001000…
12649 #define RCC_PLL1CFGR_PLL1M_5 (0x20UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00002000…
Dstm32h562xx.h13321 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
13322 #define RCC_PLL1CFGR_PLL1M_Msk (0x3FUL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00003F00…
13324 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
13325 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
13326 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
13327 #define RCC_PLL1CFGR_PLL1M_3 (0x08UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000800…
13328 #define RCC_PLL1CFGR_PLL1M_4 (0x10UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00001000…
13329 #define RCC_PLL1CFGR_PLL1M_5 (0x20UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00002000…
Dstm32h533xx.h13160 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
13161 #define RCC_PLL1CFGR_PLL1M_Msk (0x3FUL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00003F00…
13163 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
13164 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
13165 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
13166 #define RCC_PLL1CFGR_PLL1M_3 (0x08UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000800…
13167 #define RCC_PLL1CFGR_PLL1M_4 (0x10UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00001000…
13168 #define RCC_PLL1CFGR_PLL1M_5 (0x20UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00002000…
Dstm32h573xx.h15924 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
15925 #define RCC_PLL1CFGR_PLL1M_Msk (0x3FUL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00003F00…
15927 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
15928 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
15929 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
15930 #define RCC_PLL1CFGR_PLL1M_3 (0x08UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000800…
15931 #define RCC_PLL1CFGR_PLL1M_4 (0x10UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00001000…
15932 #define RCC_PLL1CFGR_PLL1M_5 (0x20UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00002000…
Dstm32h563xx.h15405 #define RCC_PLL1CFGR_PLL1M_Pos (8U) macro
15406 #define RCC_PLL1CFGR_PLL1M_Msk (0x3FUL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00003F00…
15408 #define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100…
15409 #define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200…
15410 #define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400…
15411 #define RCC_PLL1CFGR_PLL1M_3 (0x08UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000800…
15412 #define RCC_PLL1CFGR_PLL1M_4 (0x10UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00001000…
15413 #define RCC_PLL1CFGR_PLL1M_5 (0x20UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00002000…
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h4329 …->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | (PLL1M << RCC_PLL1CFGR_PLL1M_Pos)); in LL_RCC_PLL1_ConfigDomain_SYS()
4457 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, PLL1M << RCC_PLL1CFGR_PLL1M_Pos); in LL_RCC_PLL1_SetM()
4467 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); in LL_RCC_PLL1_GetM()
Dstm32h5xx_hal_rcc.h4579 … ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) | ((__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos));\
4611 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos)

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