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Searched refs:RCC_CFGR_MCOPRE_DIV2 (Results 1 – 25 of 109) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_rcc.h269 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_rcc.h292 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_rcc.h326 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_rcc.h286 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_rcc.h292 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h3532 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3552 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l010x8.h3235 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3255 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l010xb.h3243 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3263 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l011xx.h3332 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3352 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l021xx.h3460 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3480 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l031xx.h3404 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3424 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l051xx.h3476 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3496 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l010x4.h3223 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3243 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l010x6.h3236 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3256 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l081xx.h3656 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3676 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l071xx.h3528 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3548 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l052xx.h3777 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3797 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l062xx.h3905 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3925 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Dstm32l053xx.h3921 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3941 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_rcc.h363 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l152xb.h4074 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
4081 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
Dstm32l152xba.h4073 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
4080 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
Dstm32l100xba.h4067 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
4074 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
Dstm32l100xb.h4056 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
4063 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
Dstm32l151xb.h3941 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided … macro
3948 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2

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