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Searched refs:RCC_CFGR_HPRE_Pos (Results 1 – 25 of 233) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l0xx/drivers/src/
Dstm32l0xx_hal_rcc.c445 …lock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; in HAL_RCC_OscConfig()
521 >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; in HAL_RCC_OscConfig()
1023 …lock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; in HAL_RCC_ClockConfig()
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_hal_rcc.c787 >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); in HAL_RCC_ClockConfig()
993 >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); in HAL_RCC_GetHCLKFreq()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_hal_rcc.c505 >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; in HAL_RCC_OscConfig()
951 …lock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; in HAL_RCC_ClockConfig()
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dsystem_stm32c0xx.c230 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_hal_rcc.c397 … >> RCC_CFGR_HPRE_Pos] & 0x1FU); in HAL_RCC_OscConfig()
1020 >> RCC_CFGR_HPRE_Pos] & 0x1FU); in HAL_RCC_ClockConfig()
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dsystem_stm32g0xx.c286 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dsystem_stm32l0xx.c255 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; in SystemCoreClockUpdate()
Dstm32l041xx.h3397 #define RCC_CFGR_HPRE_Pos (4U) macro
3398 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
3400 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
3401 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
3402 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
3403 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32l010x8.h3100 #define RCC_CFGR_HPRE_Pos (4U) macro
3101 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
3103 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
3104 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
3105 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
3106 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32l010xb.h3108 #define RCC_CFGR_HPRE_Pos (4U) macro
3109 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
3111 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
3112 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
3113 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
3114 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32l011xx.h3197 #define RCC_CFGR_HPRE_Pos (4U) macro
3198 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
3200 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
3201 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
3202 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
3203 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32l021xx.h3325 #define RCC_CFGR_HPRE_Pos (4U) macro
3326 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
3328 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
3329 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
3330 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
3331 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32l031xx.h3269 #define RCC_CFGR_HPRE_Pos (4U) macro
3270 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
3272 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
3273 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
3274 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
3275 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32l051xx.h3341 #define RCC_CFGR_HPRE_Pos (4U) macro
3342 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
3344 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
3345 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
3346 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
3347 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32l010x4.h3088 #define RCC_CFGR_HPRE_Pos (4U) macro
3089 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
3091 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
3092 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
3093 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
3094 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dsystem_stm32wlxx.c341 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dsystem_stm32wbxx.c355 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dsystem_stm32u0xx.c330 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU]; in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h834 #define RCC_CFGR_HPRE_Pos (4U) macro
835 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
837 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
838 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
839 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
840 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32f101xb.h849 #define RCC_CFGR_HPRE_Pos (4U) macro
850 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
852 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
853 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
854 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
855 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32f100xb.h909 #define RCC_CFGR_HPRE_Pos (4U) macro
910 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
912 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
913 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
914 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
915 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_rcc.c479 …SysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); in HAL_RCC_OscConfig()
1281 …SysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); in HAL_RCC_ClockConfig()
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h2807 #define RCC_CFGR_HPRE_Pos (4U) macro
2808 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
2810 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
2811 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
2812 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
2813 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32f030x8.h2837 #define RCC_CFGR_HPRE_Pos (4U) macro
2838 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
2840 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
2841 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
2842 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
2843 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Dstm32f070x6.h2861 #define RCC_CFGR_HPRE_Pos (4U) macro
2862 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
2864 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
2865 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
2866 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
2867 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */

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