Searched refs:RCC_CDCFGR1_HPRE_Pos (Results 1 – 14 of 14) sorted by relevance
428 …m_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); in SystemCoreClockUpdate()
1227 …_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); in HAL_RCC_ClockConfig()1498 …_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); in HAL_RCC_GetHCLKFreq()
160 …m_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); in HAL_Init()
1067 …equency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
3157 …_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); in HAL_RCCEx_GetD1SysClockFreq()
405 …reClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); in SystemCoreClockUpdate()
433 …m_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); in SystemCoreClockUpdate()
12844 #define RCC_CDCFGR1_HPRE_Pos (0U) macro12845 #define RCC_CDCFGR1_HPRE_Msk (0xFUL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x0000000F */12847 #define RCC_CDCFGR1_HPRE_0 (0x1UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000001 */12848 #define RCC_CDCFGR1_HPRE_1 (0x2UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000002 */12849 #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */12850 #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
13288 #define RCC_CDCFGR1_HPRE_Pos (0U) macro13289 #define RCC_CDCFGR1_HPRE_Msk (0xFUL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x0000000F */13291 #define RCC_CDCFGR1_HPRE_0 (0x1UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000001 */13292 #define RCC_CDCFGR1_HPRE_1 (0x2UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000002 */13293 #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */13294 #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
13300 #define RCC_CDCFGR1_HPRE_Pos (0U) macro13301 #define RCC_CDCFGR1_HPRE_Msk (0xFUL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x0000000F */13303 #define RCC_CDCFGR1_HPRE_0 (0x1UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000001 */13304 #define RCC_CDCFGR1_HPRE_1 (0x2UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000002 */13305 #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */13306 #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
12856 #define RCC_CDCFGR1_HPRE_Pos (0U) macro12857 #define RCC_CDCFGR1_HPRE_Msk (0xFUL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x0000000F */12859 #define RCC_CDCFGR1_HPRE_0 (0x1UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000001 */12860 #define RCC_CDCFGR1_HPRE_1 (0x2UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000002 */12861 #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */12862 #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
13295 #define RCC_CDCFGR1_HPRE_Pos (0U) macro13296 #define RCC_CDCFGR1_HPRE_Msk (0xFUL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x0000000F */13298 #define RCC_CDCFGR1_HPRE_0 (0x1UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000001 */13299 #define RCC_CDCFGR1_HPRE_1 (0x2UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000002 */13300 #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */13301 #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
13307 #define RCC_CDCFGR1_HPRE_Pos (0U) macro13308 #define RCC_CDCFGR1_HPRE_Msk (0xFUL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x0000000F */13310 #define RCC_CDCFGR1_HPRE_0 (0x1UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000001 */13311 #define RCC_CDCFGR1_HPRE_1 (0x2UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000002 */13312 #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */13313 #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
1508 …) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))
