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Searched refs:RCC_CCIPR1_USART1SEL_Pos (Results 1 – 25 of 27) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h462 #define LL_RCC_USART1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U)| (RCC_CCIPR1_USART1SEL_Pos …
463 … ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_0 >> RCC…
464 … ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_1 >> RCC…
465 … ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL >> RCC_…
795 #define LL_RCC_USART1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART1SEL_Pos <…
796 … (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< USART1 Clock source selection */
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h555 …E_PCLK2 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, 0x000000…
556 …E_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIP…
558 …E_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIP…
560 …E_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIP…
561 …E_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIP…
562 …E_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIP…
994 …URCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, 0x000000…
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h6426 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
6427 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003…
6429 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
6430 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
Dstm32wba52xx.h10275 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
10276 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003…
10278 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
10279 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
Dstm32wba54xx.h10583 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
10584 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003…
10586 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
10587 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
Dstm32wba5mxx.h10601 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
10602 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003…
10604 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
10605 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
Dstm32wba55xx.h10601 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
10602 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003…
10604 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
10605 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h9194 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
9195 #define RCC_CCIPR1_USART1SEL_Msk (0x7UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000007…
9197 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
9198 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
9199 #define RCC_CCIPR1_USART1SEL_2 (0x4UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000004…
Dstm32h523xx.h13621 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
13622 #define RCC_CCIPR1_USART1SEL_Msk (0x7UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000007…
13624 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
13625 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
13626 #define RCC_CCIPR1_USART1SEL_2 (0x4UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000004…
Dstm32h562xx.h14511 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
14512 #define RCC_CCIPR1_USART1SEL_Msk (0x7UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000007…
14514 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
14515 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
14516 #define RCC_CCIPR1_USART1SEL_2 (0x4UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000004…
Dstm32h533xx.h14170 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
14171 #define RCC_CCIPR1_USART1SEL_Msk (0x7UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000007…
14173 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
14174 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
14175 #define RCC_CCIPR1_USART1SEL_2 (0x4UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000004…
Dstm32h573xx.h17153 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
17154 #define RCC_CCIPR1_USART1SEL_Msk (0x7UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000007…
17156 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
17157 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
17158 #define RCC_CCIPR1_USART1SEL_2 (0x4UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000004…
Dstm32h563xx.h16604 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
16605 #define RCC_CCIPR1_USART1SEL_Msk (0x7UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000007…
16607 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001…
16608 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002…
16609 #define RCC_CCIPR1_USART1SEL_2 (0x4UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000004…
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h12056 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
12057 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos)/*!< 0x00000003 */
12059 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos)/*!< 0x00000001 */
12060 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos)/*!< 0x00000002 */
Dstm32l562xx.h12786 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
12787 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos)/*!< 0x00000003 */
12789 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos)/*!< 0x00000001 */
12790 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos)/*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h15613 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
15614 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
15616 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
15617 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
Dstm32u535xx.h15064 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
15065 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
15067 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
15068 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
Dstm32u575xx.h16568 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
16569 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
16571 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
16572 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
Dstm32u585xx.h17175 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
17176 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
17178 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
17179 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
Dstm32u595xx.h17653 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
17654 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
17656 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
17657 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
Dstm32u5a5xx.h18260 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
18261 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
18263 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
18264 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
Dstm32u5f7xx.h19243 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
19244 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
19246 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
19247 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
Dstm32u599xx.h21421 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
21422 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
21424 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
21425 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
Dstm32u5g7xx.h19850 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
19851 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
19853 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
19854 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
Dstm32u5f9xx.h22381 #define RCC_CCIPR1_USART1SEL_Pos (0U) macro
22382 #define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
22384 #define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…
22385 #define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x0000000…

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