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Searched refs:RCC_APB2ENR_TIM10EN (Results 1 – 25 of 72) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h1582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1589 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1639 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
1643 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
2570 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
2572 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
2578 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
2595 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
2602 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
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Dstm32f4xx_ll_bus.h308 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc.h869 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
871 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
905 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1186 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != 0U)
1193 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == 0U)
Dstm32l1xx_ll_bus.h152 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc_ex.h1296 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1298 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1311 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1370 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
1371 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Dstm32f1xx_ll_bus.h197 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h988 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
990 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1011 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1035 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))!= RESET)
1049 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))== RESET)
Dstm32f2xx_ll_bus.h172 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h1307 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1309 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1419 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1674 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
1715 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Dstm32f7xx_ll_bus.h214 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101xg.h1604 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 Timer clo… macro
/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l152xb.h4299 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l152xba.h4307 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l100xba.h4295 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l100xb.h4275 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l151xb.h4163 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l151xba.h4186 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l100xc.h4406 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l151xc.h4465 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l151xca.h4493 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l151xdx.h4546 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l151xe.h4546 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
Dstm32l152xc.h4580 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface… macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f401xc.h4370 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk macro
Dstm32f401xe.h4370 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk macro

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