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Searched refs:RCC_APB2ENR_ADC1EN (Results 1 – 25 of 130) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc.h535 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
537 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
570 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
598 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
599 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Dstm32f1xx_ll_bus.h174 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc.h806 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
808 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
855 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
874 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
882 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Dstm32f0xx_ll_bus.h157 #define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc.h585 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
587 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
622 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
641 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
650 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Dstm32f4xx_ll_bus.h288 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_bus.h186 #if defined(RCC_APB2ENR_ADC1EN)
187 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
Dstm32f3xx_hal_rcc_ex.h2353 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
2355 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
2394 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
2657 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
2664 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc.h883 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
885 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
907 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
1188 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != 0U)
1195 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == 0U)
Dstm32l1xx_ll_bus.h154 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h938 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
940 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
1004 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
1028 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))!= RESET)
1042 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))== RESET)
Dstm32f2xx_ll_bus.h165 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc_ex.h859 #define __HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
867 #define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
879 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN) != 0U)
887 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN) == 0U)
Dstm32l0xx_ll_bus.h155 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h1251 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
1253 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
1412 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
1667 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
1708 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Dstm32f7xx_ll_bus.h203 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h1138 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface… macro
Dstm32f101xb.h1168 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface… macro
Dstm32f100xb.h1249 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface… macro
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h3108 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable… macro
Dstm32f030x8.h3140 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable… macro
Dstm32f070x6.h3173 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable… macro
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h3790 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ macro
Dstm32l010x8.h3489 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ macro
Dstm32l010xb.h3511 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ macro

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