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Searched refs:RCC_APB1ENR_TIM5EN (Results 1 – 25 of 77) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc_ex.h849 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
851 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
903 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
954 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
956 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
1008 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
1096 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1097 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
1122 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1123 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Dstm32f1xx_ll_bus.h144 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc_ex.h267 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
269 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
272 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
678 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U)
679 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U)
Dstm32l1xx_ll_bus.h112 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc.h470 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
472 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
518 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
536 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
544 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Dstm32f4xx_ll_bus.h194 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h677 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
679 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
819 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
853 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))!= RESET)
877 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))== RESET)
Dstm32f2xx_ll_bus.h133 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc_ex.h2145 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
2147 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
2216 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
2557 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
2570 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Dstm32f3xx_ll_bus.h123 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h943 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
945 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
1163 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
1586 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1613 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Dstm32f7xx_ll_bus.h151 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f100xe.h1639 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock e… macro
Dstm32f101xg.h1650 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock e… macro
Dstm32f101xe.h1598 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock e… macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h4612 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk macro
Dstm32f410rx.h4616 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk macro
Dstm32f410tx.h4593 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk macro
Dstm32f401xc.h4314 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk macro
Dstm32f401xe.h4314 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk macro
/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l151xc.h4491 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock e… macro
Dstm32l151xca.h4519 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock e… macro
Dstm32l151xdx.h4572 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock e… macro
Dstm32l151xe.h4572 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock e… macro
Dstm32l152xc.h4606 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock e… macro

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