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Searched refs:RCC_APB1ENR_I2C3EN (Results 1 – 25 of 60) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h1442 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1444 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1451 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
1480 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
1499 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
2457 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2459 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2466 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2493 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
2510 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
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Dstm32f4xx_ll_bus.h239 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc_ex.h2034 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2036 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2043 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2279 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2281 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2285 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2518 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
2523 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
2613 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
2615 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Dstm32f3xx_ll_bus.h175 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h782 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
784 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
834 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
868 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))!= RESET)
892 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))== RESET)
Dstm32f2xx_ll_bus.h148 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc_ex.h787 #define __HAL_RCC_I2C3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
802 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
817 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) != 0U)
831 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) == 0U)
Dstm32l0xx_ll_bus.h135 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h1086 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1088 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1187 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
1604 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
1631 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Dstm32f7xx_ll_bus.h170 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l081xx.h4005 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enab… macro
Dstm32l071xx.h3871 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enab… macro
Dstm32l072xx.h4315 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enab… macro
Dstm32l073xx.h4463 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enab… macro
Dstm32l083xx.h4597 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enab… macro
Dstm32l082xx.h4449 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enab… macro
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h5120 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C 3 clock ena… macro
Dstm32f318xx.h5113 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C 3 clock ena… macro
Dstm32f302x8.h8748 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C 3 clock ena… macro
Dstm32f302xe.h10631 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C 3 clock ena… macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f401xc.h4335 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk macro
Dstm32f401xe.h4335 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk macro
Dstm32f411xe.h4347 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk macro
Dstm32f405xx.h9710 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk macro
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h9553 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk macro

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