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Searched refs:RCC_APB1ENR1_TIM5EN (Results 1 – 25 of 52) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h844 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
846 … tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
1034 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
1407 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
1467 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
Dstm32g4xx_ll_bus.h140 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h963 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
965 … tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
1178 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
1501 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
1558 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
Dstm32l5xx_ll_bus.h129 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h1096 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
1098 … tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
1355 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
1899 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
1998 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
Dstm32l4xx_ll_bus.h178 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_rcc.h1482 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
1484 … tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
1649 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
2351 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
2405 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
Dstm32u5xx_ll_bus.h218 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_bus.h165 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
Dstm32h7rsxx_hal_rcc.h1367 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN);\
1579 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
2083 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_bus.h255 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g473xx.h8826 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32g483xx.h9053 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32g474xx.h12399 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32g484xx.h12626 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l471xx.h11020 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32l475xx.h11184 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32l476xx.h11216 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32l486xx.h11432 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32l485xx.h11406 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32l4a6xx.h12562 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32l496xx.h12228 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32l4r5xx.h12452 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
Dstm32l4r7xx.h12942 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h11737 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk macro

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