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Searched refs:RCC_AHBSMENR_DMA1SMEN (Results 1 – 25 of 41) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc.h942 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
947 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
1021 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != …
1025 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == …
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h1266 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1271 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1401 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) !=…
1406 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) =…
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h1940 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1953 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
2187 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) !=…
2200 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) =…
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h1744 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1764 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h3854 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l010x8.h3554 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l010xb.h3580 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l011xx.h3619 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l021xx.h3756 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l031xx.h3717 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l051xx.h3825 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l010x4.h3510 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l010x6.h3543 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l081xx.h4056 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l071xx.h3919 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l052xx.h4171 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l062xx.h4308 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l053xx.h4321 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l072xx.h4369 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l073xx.h4517 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l083xx.h4654 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
Dstm32l063xx.h4456 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled i… macro
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h4150 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk macro
Dstm32c031xx.h4313 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk macro
Dstm32c071xx.h4781 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk macro

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