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Searched refs:RCC_AHB3ENR_QSPIEN (Results 1 – 25 of 66) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h1278 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
1280 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
1283 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
1300 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
1301 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
4135 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4137 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4142 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
4155 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
4158 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
[all …]
Dstm32f4xx_ll_bus.h174 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h790 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
792 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
802 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
1377 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
1385 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
Dstm32g4xx_ll_bus.h126 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h1010 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
1012 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
1042 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
1849 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
1865 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
Dstm32l4xx_ll_bus.h154 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc.h802 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
804 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
879 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
914 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U)
943 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U)
2683 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
2685 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
2704 #define __HAL_RCC_C1_QSPI_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
3710 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
3712 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
[all …]
Dstm32h7xx_ll_bus.h81 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h903 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
905 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
910 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
1573 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
1576 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
Dstm32f7xx_ll_bus.h139 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h6129 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32l412xx.h5907 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32l433xx.h9886 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32l451xx.h10047 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g4a1xx.h8349 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32g491xx.h8122 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32g473xx.h8812 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32g471xx.h8277 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h9645 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32f722xx.h9626 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f423xx.h10039 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32f412zx.h9730 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32f412rx.h9706 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32f412vx.h9714 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro
Dstm32f413xx.h9997 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk macro

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