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Searched refs:PWR_CR3_RRS (Results 1 – 25 of 78) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_pwr.h181 #define LL_PWR_FULL_SRAM_RETENTION PWR_CR3_RRS
718 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, LL_PWR_FULL_SRAM_RETENTION); in LL_PWR_EnableSRAMRetention()
728 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_DisableSRAMRetention()
738 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (LL_PWR_FULL_SRAM_RETENTION)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRAMRetention()
753 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAMSize); in LL_PWR_SetSRAMContentRetention()
765 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS)); in LL_PWR_GetSRAMContentRetention()
Dstm32u0xx_hal_pwr_ex.h266 #define PWR_FULL_SRAM_RETENTION PWR_CR3_RRS /*!< Full SRAM is powered by the low-power regulat…
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_pwr.h186 #define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS
839 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, LL_PWR_FULL_SRAM2_RETENTION); in LL_PWR_EnableSRAM2Retention()
849 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_DisableSRAM2Retention()
859 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (LL_PWR_FULL_SRAM2_RETENTION)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRAM2Retention()
876 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2Size); in LL_PWR_SetSRAM2ContentRetention()
890 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS)); in LL_PWR_GetSRAM2ContentRetention()
Dstm32l4xx_hal_pwr_ex.h292 #define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS /*!< Full SRAM2 is powered by the low-pow…
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_pwr.h755 #if defined(PWR_CR3_RRS)
763 SET_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_EnableSRAMRetention()
773 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_DisableSRAMRetention()
783 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRAMRetention()
Dstm32g0xx_hal_pwr_ex.h577 #if defined(PWR_CR3_RRS)
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_pwr.h794 SET_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_EnableSRAM2Retention()
804 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_DisableSRAM2Retention()
815 temp = READ_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_IsEnabledSRAM2Retention()
817 return ((temp == (PWR_CR3_RRS))?1U:0U); in LL_PWR_IsEnabledSRAM2Retention()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_hal_pwr_ex.c669 #if defined(PWR_CR3_RRS)
678 SET_BIT(PWR->CR3, PWR_CR3_RRS); in HAL_PWREx_EnableSRAMRetention()
690 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in HAL_PWREx_DisableSRAMRetention()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_pwr.h707 SET_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_EnableSRAM2Retention()
717 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_DisableSRAM2Retention()
727 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRAM2Retention()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_pwr.h829 SET_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_EnableSRAM2Retention()
841 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_DisableSRAM2Retention()
853 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRAM2Retention()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_pwr_ex.c757 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in HAL_PWREx_SetSRAM2ContentRetention()
761 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, PWR_FULL_SRAM2_RETENTION); in HAL_PWREx_SetSRAM2ContentRetention()
766 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, PWR_4KBYTES_SRAM2_RETENTION); in HAL_PWREx_SetSRAM2ContentRetention()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_hal_pwr_ex.c971 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, PWR_FULL_SRAM_RETENTION); in HAL_PWREx_EnableSRAMContentRetention()
980 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in HAL_PWREx_DisableSRAMContentRetention()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_pwr_ex.c562 SET_BIT(PWR->CR3, PWR_CR3_RRS); in HAL_PWREx_EnableSRAM2ContentRetention()
574 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in HAL_PWREx_DisableSRAM2ContentRetention()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_pwr.h873 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2Retention); in LL_PWR_SetSRAM2Retention()
886 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS)); in LL_PWR_GetSRAM2Retention()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_pwr_ex.c548 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2ContentRetention); in HAL_PWREx_ConfigSRAM2ContentRetention()
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g031xx.h3761 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< RAM retention i… macro
Dstm32g041xx.h3997 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< RAM retention i… macro
Dstm32g051xx.h4097 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< RAM retention i… macro
Dstm32g061xx.h4333 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< RAM retention i… macro
Dstm32g071xx.h4315 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< RAM retention i… macro
Dstm32g081xx.h4551 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< RAM retention i… macro
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h5375 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 retention… macro
Dstm32wle5xx.h5375 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 retention… macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h4424 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< Ram retention i… macro
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h5888 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 retention… macro

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