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Searched refs:PWR_CR1_LPMS_STOP2_Msk (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h4989 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
4990 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l412xx.h4773 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
4774 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l433xx.h8554 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
8555 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l451xx.h8728 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
8729 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l442xx.h8690 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
8691 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l431xx.h8471 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
8472 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l432xx.h8474 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
8475 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l443xx.h8770 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
8771 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l471xx.h9426 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
9427 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l452xx.h8788 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
8789 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l462xx.h9004 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
9005 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l475xx.h9581 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
9582 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l476xx.h9604 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
9605 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l486xx.h9820 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
9821 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l485xx.h9797 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
9798 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l4a6xx.h10714 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
10715 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l496xx.h10392 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
10393 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l4r5xx.h10564 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
10565 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l4r7xx.h11045 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
11046 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l4s5xx.h10893 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
10894 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l4s7xx.h11374 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
11375 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l4p5xx.h11338 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
11339 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l4q5xx.h11831 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
11832 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l4r9xx.h14164 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
14165 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Dstm32l4s9xx.h14493 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ macro
14494 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */