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Searched refs:PWR_CPUCR_CSSF (Results 1 – 25 of 31) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_pwr.h369 … ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)) : \
370 … ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)) : \
371 (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)))
Dstm32n6xx_ll_pwr.h1635 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); in LL_PWR_ClearFlag_STOP_SB()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_pwr.h502 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \
516 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
Dstm32h7xx_ll_pwr.h71 #define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /*!< Clear flags for CPU */
2188 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); in LL_PWR_ClearFlag_CPU()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_pwr_ex.c1114 SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); in HAL_PWREx_ClearDomainFlags()
1125 SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); in HAL_PWREx_ClearDomainFlags()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h12456 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h7b0xx.h12900 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h7b0xxq.h12912 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h7a3xxq.h12468 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h7b3xx.h12907 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h7b3xxq.h12919 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h730xxq.h14792 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h733xx.h14780 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h725xx.h14341 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h730xx.h14780 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h735xx.h14792 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h742xx.h13628 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h723xx.h14329 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h750xx.h14521 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h753xx.h14527 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h745xx.h14796 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h745xg.h14796 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h743xx.h14258 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h755xx.h15065 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro
Dstm32h757xx.h18222 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain… macro

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