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Searched refs:PLLP1 (Results 1 – 5 of 5) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_utils.c258 assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP1)); in LL_PLL_ConfigSystemClock_HSI()
276 pUTILS_PLLInitStruct->PLLP1, pUTILS_PLLInitStruct->PLLP2); in LL_PLL_ConfigSystemClock_HSI()
278 …assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq * pUTILS_PLLInitStruct->PLLP1 * pUTILS_PLLInitStruc… in LL_PLL_ConfigSystemClock_HSI()
344 assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP1)); in LL_PLL_ConfigSystemClock_MSI()
360 pUTILS_PLLInitStruct->PLLP1, pUTILS_PLLInitStruct->PLLP2); in LL_PLL_ConfigSystemClock_MSI()
363 …assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq * pUTILS_PLLInitStruct->PLLP1 * pUTILS_PLLInitStruc… in LL_PLL_ConfigSystemClock_MSI()
437 assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP1)); in LL_PLL_ConfigSystemClock_HSE()
453 pUTILS_PLLInitStruct->PLLP1, pUTILS_PLLInitStruct->PLLP2); in LL_PLL_ConfigSystemClock_HSE()
456 …assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq * pUTILS_PLLInitStruct->PLLP1 * pUTILS_PLLInitStruc… in LL_PLL_ConfigSystemClock_HSE()
530 LL_RCC_PLL1_SetP1(pUTILS_PLLInitStruct->PLLP1); in UTILS_ConfigurePLL1InIntegerMode()
Dstm32n6xx_hal_rcc.c1673 …pRCC_OscInitStruct->PLL1.PLLP1 = ((cfgr_value & RCC_PLL1CFGR3_PLL1PDIV1) >> RCC_PLL1CFGR3_PLL1PDIV… in HAL_RCC_GetOscConfig()
1700 …pRCC_OscInitStruct->PLL2.PLLP1 = ((cfgr_value & RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV… in HAL_RCC_GetOscConfig()
1727 …pRCC_OscInitStruct->PLL3.PLLP1 = ((cfgr_value & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV… in HAL_RCC_GetOscConfig()
1754 …pRCC_OscInitStruct->PLL4.PLLP1 = ((cfgr_value & RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV… in HAL_RCC_GetOscConfig()
2044 assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP1)); in RCC_PLL_Config()
2073 …((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Po… in RCC_PLL_Config()
2231 …((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Po… in RCC_PLL_IsNewConfig()
Dstm32n6xx_hal_rcc_ex.c3161 assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP1)); in HAL_RCCEx_PLLSSCGConfig()
3191 …((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Po… in HAL_RCCEx_PLLSSCGConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_utils.h111 uint32_t PLLP1; /*!< Division factor level 1 for PLL VCO output clock. member
Dstm32n6xx_hal_rcc.h69 uint32_t PLLP1; /*!< Division factor P1 for system clock. member