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Searched refs:PLL4CFGR3 (Results 1 – 11 of 11) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h6105 SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSRST); in LL_RCC_PLL4_AssertModulationSpreadSpectrumReset()
6116 CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSRST); in LL_RCC_PLL4_ReleaseModulationSpreadSpectrumReset()
6127 SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN); in LL_RCC_PLL4_EnableDAC()
6138 CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN); in LL_RCC_PLL4_DisableDAC()
6148 …return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN) == RCC_PLL4CFGR3_PLL4DACEN) ? 1UL : 0UL… in LL_RCC_PLL4_IsEnabledDAC()
6159 CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS); in LL_RCC_PLL4_EnableModulationSpreadSpectrum()
6170 SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS); in LL_RCC_PLL4_DisableModulationSpreadSpectrum()
6180 return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS) == 0UL) ? 1UL : 0UL); in LL_RCC_PLL4_IsEnabledModulationSpreadSpectrum()
6191 SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN); in LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum()
6202 CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN); in LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum()
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Dstm32n6xx_hal_rcc_ex.h1178 …MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL4CFGR3_PL…
1189 …MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL4CFGR…
Dstm32n6xx_hal_rcc.h3949 MODIFY_REG(RCC->PLL4CFGR3, (RCC_PLL4CFGR3_PLL4PDIV1 | RCC_PLL4CFGR3_PLL4PDIV2), \
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c358 pllcfgr = READ_REG(RCC->PLL4CFGR3); in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c415 pllcfgr = READ_REG(RCC->PLL4CFGR3); in SystemCoreClockUpdate()
Dstm32n645xx.h1945 …__IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 … member
Dstm32n657xx.h2071 …__IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 … member
Dstm32n655xx.h2043 …__IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 … member
Dstm32n647xx.h1973 …__IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 … member
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c293 WRITE_REG(RCC->PLL4CFGR3, 0x49000005U); in HAL_RCC_DeInit()
1753 cfgr_value = RCC->PLL4CFGR3; in HAL_RCC_GetOscConfig()
Dstm32n6xx_ll_rcc.c246 WRITE_REG(RCC->PLL4CFGR3, 0x49000005U); in LL_RCC_DeInit()