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Searched refs:PLL2CFGR (Results 1 – 25 of 29) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h4379 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ in LL_RCC_PLL2_ConfigDomain_48M()
4406 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ in LL_RCC_PLL2_ConfigDomain_SAI()
4433 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ in LL_RCC_PLL2_ConfigDomain_ADC()
4452 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, PLL2Source); in LL_RCC_PLL2_SetSource()
4466 return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC)); in LL_RCC_PLL2_GetSource()
4564 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M, (PLL2M - 1UL) << RCC_PLL2CFGR_PLL2M_Pos); in LL_RCC_PLL2_SetDivider()
4574 return (uint32_t)((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1UL); in LL_RCC_PLL2_GetDivider()
4584 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); in LL_RCC_PLL2_EnableDomain_SAI()
4596 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); in LL_RCC_PLL2_DisableDomain_SAI()
4606 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN) == (RCC_PLL2CFGR_PLL2PEN)) ? 1UL : 0UL); in LL_RCC_PLL2_IsEnabledDomain_SAI()
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Dstm32u5xx_hal_rcc_ex.h1182 #define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2…
1193 #define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC))
1221 …MODIFY_REG(RCC->PLL2CFGR,(RCC_PLL2CFGR_PLL2SRC|RCC_PLL2CFGR_PLL2M), ((__PLL2SOURCE__)<< RCC_PLL2CF…
1245 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__))
1246 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT_…
1260 #define __HAL_RCC_GET_PLL2CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOU…
1267 #define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN)
1268 #define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN)
1292 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__))
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h4600 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, PLL2Source); in LL_RCC_PLL2_SetSource()
4614 return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC)); in LL_RCC_PLL2_GetSource()
4625 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M, PLL2M << RCC_PLL2CFGR_PLL2M_Pos); in LL_RCC_PLL2_SetM()
4635 return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos); in LL_RCC_PLL2_GetM()
4732 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); in LL_RCC_PLL2P_Enable()
4744 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); in LL_RCC_PLL2P_Disable()
4754 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); in LL_RCC_PLL2Q_Enable()
4766 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); in LL_RCC_PLL2Q_Disable()
4776 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); in LL_RCC_PLL2R_Enable()
4788 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); in LL_RCC_PLL2R_Disable()
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Dstm32h5xx_hal_rcc_ex.h1397 #define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2…
1408 #define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC))
1443 MODIFY_REG(RCC->PLL2CFGR, (RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M), \
1481 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_DIVM2, (__PLL2M__) << RCC_PLL2CFGR_DIVM2_Pos)
1551 #define __HAL_RCC_PLL2_CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__…
1552 #define __HAL_RCC_PLL2_CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT…
1565 #define __HAL_RCC_GET_PLL2_CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKO…
1572 #define __HAL_RCC_PLL2_FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN)
1573 #define __HAL_RCC_PLL2_FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN)
1602 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__))
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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc_ex.c1333 …pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFG… in HAL_RCCEx_GetPeriphCLKConfig()
1334 …pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M… in HAL_RCCEx_GetPeriphCLKConfig()
1339 …pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_P… in HAL_RCCEx_GetPeriphCLKConfig()
1597 pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC); in HAL_RCCEx_GetPLL2ClockFreq()
1598 pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U; in HAL_RCCEx_GetPLL2ClockFreq()
1599 pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos); in HAL_RCCEx_GetPLL2ClockFreq()
3197 …CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_… in HAL_RCCEx_DisablePLL2()
Dstm32u5xx_hal_rcc.c465 CLEAR_REG(RCC->PLL2CFGR); in HAL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc_ex.c2545 …pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFG… in HAL_RCCEx_GetPeriphCLKConfig()
2546 …pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M… in HAL_RCCEx_GetPeriphCLKConfig()
2551 …pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_P… in HAL_RCCEx_GetPeriphCLKConfig()
2929 pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC); in HAL_RCCEx_GetPLL2ClockFreq()
2930 pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos); in HAL_RCCEx_GetPLL2ClockFreq()
2931 pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos); in HAL_RCCEx_GetPLL2ClockFreq()
5397 …CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_… in HAL_RCCEx_DisablePLL2()
Dstm32h5xx_hal_rcc.c387 CLEAR_REG(RCC->PLL2CFGR); in HAL_RCC_DeInit()
Dstm32h5xx_ll_rcc.c259 CLEAR_REG(RCC->PLL2CFGR); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dsystem_stm32h5xx.c227 RCC->PLL2CFGR = 0U; in SystemInit()
Dsystem_stm32h5xx_s.c240 RCC->PLL2CFGR = 0U; in SystemInit()
Dstm32h503xx.h715 …__IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register … member
Dstm32h523xx.h878 …__IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register … member
Dstm32h562xx.h925 …__IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register … member
Dstm32h533xx.h942 …__IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register … member
Dstm32h573xx.h1167 …__IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register … member
Dstm32h563xx.h1103 …__IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register … member
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h957 …__IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register … member
Dstm32u535xx.h891 …__IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register … member
Dstm32u575xx.h957 …__IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register … member
Dstm32u585xx.h1024 …__IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register … member
Dstm32u595xx.h998 …__IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register … member
Dstm32u5a5xx.h1065 …__IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register … member
Dstm32u5f7xx.h1160 …__IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register … member
Dstm32u599xx.h1179 …__IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register … member

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