Home
last modified time | relevance | path

Searched refs:PLL1CFGR3 (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h5055 SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSRST); in LL_RCC_PLL1_AssertModulationSpreadSpectrumReset()
5066 CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSRST); in LL_RCC_PLL1_ReleaseModulationSpreadSpectrumReset()
5077 SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN); in LL_RCC_PLL1_EnableDAC()
5088 CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN); in LL_RCC_PLL1_DisableDAC()
5098 …return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN) == RCC_PLL1CFGR3_PLL1DACEN) ? 1UL : 0UL… in LL_RCC_PLL1_IsEnabledDAC()
5109 CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS); in LL_RCC_PLL1_EnableModulationSpreadSpectrum()
5120 SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS); in LL_RCC_PLL1_DisableModulationSpreadSpectrum()
5130 return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS) == 0UL) ? 1UL : 0UL); in LL_RCC_PLL1_IsEnabledModulationSpreadSpectrum()
5141 SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN); in LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum()
5152 CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN); in LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum()
[all …]
Dstm32n6xx_hal_rcc_ex.h1109 …MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL1CFGR3_PL…
1120 …MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL1CFGR…
Dstm32n6xx_hal_rcc.h3641 MODIFY_REG(RCC->PLL1CFGR3, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c281 WRITE_REG(RCC->PLL1CFGR3, 0x4900000DU); in HAL_RCC_DeInit()
1672 cfgr_value = RCC->PLL1CFGR3; in HAL_RCC_GetOscConfig()
2034 p_rcc_pll_cfgr3_reg = &(RCC->PLL1CFGR3) + (((uint32_t)0x4) * PLLnumber); in RCC_PLL_Config()
2214 p_rcc_pll_cfgr3_reg = &(RCC->PLL1CFGR3) + (((uint32_t)0x4) * PLLnumber); in RCC_PLL_IsNewConfig()
Dstm32n6xx_ll_rcc.c234 WRITE_REG(RCC->PLL1CFGR3, 0x4900000DU); in LL_RCC_DeInit()
Dstm32n6xx_hal_rcc_ex.c3152 p_rcc_pll_cfgr3_reg = &(RCC->PLL1CFGR3) + (((uint32_t)0x4) * PLLnumber); in HAL_RCCEx_PLLSSCGConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c314 pllcfgr = READ_REG(RCC->PLL1CFGR3); in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c371 pllcfgr = READ_REG(RCC->PLL1CFGR3); in SystemCoreClockUpdate()
Dstm32n645xx.h1933 …__IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 … member
Dstm32n657xx.h2059 …__IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 … member
Dstm32n655xx.h2031 …__IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 … member
Dstm32n647xx.h1961 …__IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 … member