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Searched refs:OPAMP1_CSR_VPSEL_Pos (Results 1 – 25 of 79) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f302xc.h2439 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
2440 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
2442 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
2443 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f358xx.h2725 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
2726 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
2728 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
2729 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f303xc.h2767 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
2768 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
2770 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
2771 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f302xe.h2462 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
2463 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
2465 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
2466 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f303xe.h2765 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
2766 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
2768 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
2769 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f398xx.h2721 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
2722 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
2724 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
2725 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h12071 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
12072 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
12074 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
12075 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h7b0xx.h12394 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
12395 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
12397 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
12398 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h7b0xxq.h12395 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
12396 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
12398 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
12399 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h7a3xxq.h12072 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
12073 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
12075 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
12076 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h7b3xx.h12401 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
12402 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
12404 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
12405 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h7b3xxq.h12402 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
12403 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
12405 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
12406 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h730xxq.h14311 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
14312 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
14314 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
14315 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h733xx.h14310 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
14311 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
14313 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
14314 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h725xx.h13981 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
13982 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
13984 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
13985 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h730xx.h14310 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
14311 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
14313 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
14314 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h735xx.h14311 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
14312 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
14314 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
14315 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h742xx.h13338 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
13339 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
13341 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
13342 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h723xx.h13980 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
13981 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
13983 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
13984 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h750xx.h14231 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
14232 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
14234 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
14235 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h753xx.h14237 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
14238 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
14240 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
14241 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h745xx.h14492 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
14493 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
14495 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
14496 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32h745xg.h14492 #define OPAMP1_CSR_VPSEL_Pos (2U) macro
14493 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
14495 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
14496 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h9184 #define OPAMP1_CSR_VPSEL_Pos (10U) macro
9185 #define OPAMP1_CSR_VPSEL_Msk (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
Dstm32l412xx.h8959 #define OPAMP1_CSR_VPSEL_Pos (10U) macro
8960 #define OPAMP1_CSR_VPSEL_Msk (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */

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