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Searched refs:IfrGap (Results 1 – 14 of 14) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_ucpd.c132 (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); in LL_UCPD_Init()
148 UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ in LL_UCPD_StructInit()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_ucpd.c132 (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); in LL_UCPD_Init()
148 UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ in LL_UCPD_StructInit()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_ucpd.c132 (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); in LL_UCPD_Init()
148 UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ in LL_UCPD_StructInit()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_ucpd.c132 (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); in LL_UCPD_Init()
148 UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ in LL_UCPD_StructInit()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_ucpd.c132 (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); in LL_UCPD_Init()
148 UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ in LL_UCPD_StructInit()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_ucpd.c132 (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); in LL_UCPD_Init()
148 UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ in LL_UCPD_StructInit()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_ll_ucpd.c149 (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); in LL_UCPD_Init()
165 UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ in LL_UCPD_StructInit()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_ucpd.h67 …uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order … member
429 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) in LL_UCPD_SetIfrGap() argument
431 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_ucpd.h67 …uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order … member
431 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) in LL_UCPD_SetIfrGap() argument
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_ucpd.h67 …uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order … member
431 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) in LL_UCPD_SetIfrGap() argument
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_ucpd.h67 …uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order … member
431 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) in LL_UCPD_SetIfrGap() argument
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_ucpd.h67 …uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order … member
431 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) in LL_UCPD_SetIfrGap() argument
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_ucpd.h67 …uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order … member
431 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) in LL_UCPD_SetIfrGap() argument
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_ucpd.h67 …uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order … member
431 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) in LL_UCPD_SetIfrGap() argument
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()