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Searched refs:I2C_OAR1_ADD5_Pos (Results 1 – 25 of 63) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h4522 #define I2C_OAR1_ADD5_Pos (5U) macro
4523 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f101xb.h4584 #define I2C_OAR1_ADD5_Pos (5U) macro
4585 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f100xb.h4986 #define I2C_OAR1_ADD5_Pos (5U) macro
4987 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f102x6.h5641 #define I2C_OAR1_ADD5_Pos (5U) macro
5642 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f100xe.h5500 #define I2C_OAR1_ADD5_Pos (5U) macro
5501 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f101xg.h5633 #define I2C_OAR1_ADD5_Pos (5U) macro
5634 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f101xe.h5559 #define I2C_OAR1_ADD5_Pos (5U) macro
5560 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f102xb.h5695 #define I2C_OAR1_ADD5_Pos (5U) macro
5696 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h3696 #define I2C_OAR1_ADD5_Pos (5U) macro
3697 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f410rx.h3696 #define I2C_OAR1_ADD5_Pos (5U) macro
3697 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f410tx.h3686 #define I2C_OAR1_ADD5_Pos (5U) macro
3687 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f401xc.h3617 #define I2C_OAR1_ADD5_Pos (5U) macro
3618 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32f401xe.h3617 #define I2C_OAR1_ADD5_Pos (5U) macro
3618 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l152xb.h3483 #define I2C_OAR1_ADD5_Pos (5U) macro
3484 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l152xba.h3477 #define I2C_OAR1_ADD5_Pos (5U) macro
3478 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l100xba.h3471 #define I2C_OAR1_ADD5_Pos (5U) macro
3472 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l100xb.h3465 #define I2C_OAR1_ADD5_Pos (5U) macro
3466 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l151xb.h3466 #define I2C_OAR1_ADD5_Pos (5U) macro
3467 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l151xba.h3475 #define I2C_OAR1_ADD5_Pos (5U) macro
3476 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l100xc.h3573 #define I2C_OAR1_ADD5_Pos (5U) macro
3574 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l151xc.h3742 #define I2C_OAR1_ADD5_Pos (5U) macro
3743 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l151xca.h3758 #define I2C_OAR1_ADD5_Pos (5U) macro
3759 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l151xdx.h3805 #define I2C_OAR1_ADD5_Pos (5U) macro
3806 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l151xe.h3805 #define I2C_OAR1_ADD5_Pos (5U) macro
3806 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
Dstm32l152xc.h3738 #define I2C_OAR1_ADD5_Pos (5U) macro
3739 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */

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