Searched refs:FSMC_PCR4_TCLR_Pos (Results 1 – 10 of 10) sorted by relevance
844 (Init->TCLRSetupTime << FSMC_PCR4_TCLR_Pos) | in FSMC_PCCARD_Init()
927 (Init->TCLRSetupTime << FSMC_PCR4_TCLR_Pos) | in FSMC_PCCARD_Init()
7399 #define FSMC_PCR4_TCLR_Pos (9U) macro7400 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */7402 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */7403 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */7404 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */7405 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
7249 #define FSMC_PCR4_TCLR_Pos (9U) macro7250 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */7252 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */7253 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */7254 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */7255 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
7548 #define FSMC_PCR4_TCLR_Pos (9U) macro7549 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */7551 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */7552 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */7553 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */7554 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
7698 #define FSMC_PCR4_TCLR_Pos (9U) macro7699 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */7701 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */7702 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */7703 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */7704 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
7293 #define FSMC_PCR4_TCLR_Pos (9U) macro7294 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */7296 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */7297 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */7298 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */7299 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
7475 #define FSMC_PCR4_TCLR_Pos (9U) macro7476 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */7478 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */7479 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */7480 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */7481 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
7593 #define FSMC_PCR4_TCLR_Pos (9U) macro7594 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */7596 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */7597 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */7598 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */7599 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
7772 #define FSMC_PCR4_TCLR_Pos (9U) macro7773 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */7775 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */7776 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */7777 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */7778 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
