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Searched refs:FMC_NORSRAM_BANK1 (Results 1 – 25 of 36) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_fmc.c253 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
255 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
258 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
261 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
276 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_Init()
317 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
333 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_DeInit()
390 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
392 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
394 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
Dstm32l5xx_hal_nor.c291 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
469 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
573 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
651 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
745 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
849 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
954 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1070 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1167 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1261 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_fmc.c258 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
260 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
263 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
266 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
281 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_Init()
322 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
338 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_DeInit()
395 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
397 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
399 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
Dstm32u5xx_hal_nor.c295 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
473 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
577 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
655 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
749 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
853 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
958 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1074 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1171 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1265 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_fmc.c258 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
260 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
263 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
266 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
281 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_Init()
322 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
338 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_DeInit()
395 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
397 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
399 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
Dstm32g4xx_hal_nor.c292 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
470 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
574 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
652 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
746 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
850 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
955 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1071 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1168 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1262 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_fmc.c285 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
287 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
291 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
294 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
311 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_Init()
353 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
370 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_DeInit()
441 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
443 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
445 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
Dstm32l4xx_hal_nor.c292 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
470 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
574 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
652 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
746 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
850 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
955 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1071 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1168 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1262 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_fmc.c228 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
230 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
245 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_Init()
288 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
304 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_DeInit()
362 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
364 …tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTR1_CLKDIV_Pos… in FMC_NORSRAM_Timing_Init()
366 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_fmc.c277 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
279 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
282 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
285 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
300 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_Init()
341 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
357 case FMC_NORSRAM_BANK1 : in FMC_NORSRAM_DeInit()
414 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
416 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
418 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
Dstm32h5xx_hal_nor.c295 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
473 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
577 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
655 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
749 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
853 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
958 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1074 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1171 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1265 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_nor.c292 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
470 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
574 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
652 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
746 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
850 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
955 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1071 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1168 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1262 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
Dstm32f4xx_ll_fmc.c337 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
339 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
344 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
347 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
374 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
427 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
429 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
431 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_nor.c291 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
469 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
573 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
651 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
745 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
849 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
954 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1070 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1167 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1261 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
Dstm32f7xx_ll_fmc.c266 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
268 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
271 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
274 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
300 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
350 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
352 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
354 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_nor.c294 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
472 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
576 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
654 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
748 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
852 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
957 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1073 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1170 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1264 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
Dstm32h7xx_ll_fmc.c266 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
268 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
271 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
274 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
300 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
351 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
353 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
355 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_nor.c294 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
472 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
576 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
654 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
748 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
852 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
957 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1073 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1170 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1264 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
Dstm32n6xx_ll_fmc.c265 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
267 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_CFGR_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
293 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
346 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_CFGR_CCLKEN)) in FMC_NORSRAM_Timing_Init()
348 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
350 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_hal_nor.c292 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
470 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
574 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
652 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
746 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
850 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
955 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1071 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1168 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1262 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
Dstm32f3xx_ll_fmc.c274 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
276 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
302 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
353 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
355 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
357 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_nor.c294 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Init()
472 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_ID()
576 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReturnToReadMode()
654 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read()
748 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Program()
852 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ReadBuffer()
957 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_ProgramBuffer()
1073 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Block()
1170 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Erase_Chip()
1264 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) in HAL_NOR_Read_CFI()
Dstm32h7rsxx_ll_fmc.c271 …((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) in FMC_NORSRAM_Init()
273 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
276 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
279 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
305 if (Bank == FMC_NORSRAM_BANK1) in FMC_NORSRAM_DeInit()
356 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
358 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
360 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_fmc.h42 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
250 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) macro
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_fmc.h43 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
361 #define FMC_NORSRAM_BANK1 (0x00000000U) macro

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