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Searched refs:DMA_CTR2_TCEM_Pos (Results 1 – 25 of 31) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2329 #define DMA_CTR2_TCEM_Pos (30U) macro
2330 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
2332 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
2333 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32wba52xx.h2914 #define DMA_CTR2_TCEM_Pos (30U) macro
2915 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
2917 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
2918 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32wba54xx.h3097 #define DMA_CTR2_TCEM_Pos (30U) macro
3098 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
3100 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
3101 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32wba5mxx.h3097 #define DMA_CTR2_TCEM_Pos (30U) macro
3098 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
3100 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
3101 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32wba55xx.h3097 #define DMA_CTR2_TCEM_Pos (30U) macro
3098 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
3100 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
3101 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3932 #define DMA_CTR2_TCEM_Pos (30U) macro
3933 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
3935 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
3936 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32h523xx.h5294 #define DMA_CTR2_TCEM_Pos (30U) macro
5295 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
5297 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
5298 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32h562xx.h5737 #define DMA_CTR2_TCEM_Pos (30U) macro
5738 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
5740 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
5741 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32h533xx.h5703 #define DMA_CTR2_TCEM_Pos (30U) macro
5704 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
5706 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
5707 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32h573xx.h8230 #define DMA_CTR2_TCEM_Pos (30U) macro
8231 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
8233 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
8234 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32h563xx.h7821 #define DMA_CTR2_TCEM_Pos (30U) macro
7822 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
7824 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
7825 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6382 #define DMA_CTR2_TCEM_Pos (30U) macro
6383 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
6385 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
6386 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32u535xx.h5982 #define DMA_CTR2_TCEM_Pos (30U) macro
5983 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
5985 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
5986 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32u575xx.h6381 #define DMA_CTR2_TCEM_Pos (30U) macro
6382 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
6384 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
6385 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32u585xx.h6830 #define DMA_CTR2_TCEM_Pos (30U) macro
6831 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
6833 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
6834 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32u595xx.h6637 #define DMA_CTR2_TCEM_Pos (30U) macro
6638 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
6640 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
6641 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32u5a5xx.h7086 #define DMA_CTR2_TCEM_Pos (30U) macro
7087 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
7089 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
7090 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32u5f7xx.h6933 #define DMA_CTR2_TCEM_Pos (30U) macro
6934 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
6936 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
6937 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32u599xx.h6925 #define DMA_CTR2_TCEM_Pos (30U) macro
6926 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
6928 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
6929 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32u5g7xx.h7382 #define DMA_CTR2_TCEM_Pos (30U) macro
7383 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
7385 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
7386 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32u5f9xx.h7053 #define DMA_CTR2_TCEM_Pos (30U) macro
7054 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
7056 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
7057 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5089 #define DMA_CTR2_TCEM_Pos (30U) macro
5090 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
5092 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
5093 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32h7s7xx.h5613 #define DMA_CTR2_TCEM_Pos (30U) macro
5614 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
5616 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
5617 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32h7s3xx.h5534 #define DMA_CTR2_TCEM_Pos (30U) macro
5535 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
5537 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
5538 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
Dstm32h7r7xx.h5166 #define DMA_CTR2_TCEM_Pos (30U) macro
5167 #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000…
5169 #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
5170 #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */

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