/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 2307 #define DMA_CTR2_SWREQ_Pos (9U) macro 2308 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100…
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D | stm32wba52xx.h | 2892 #define DMA_CTR2_SWREQ_Pos (9U) macro 2893 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100…
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D | stm32wba54xx.h | 3075 #define DMA_CTR2_SWREQ_Pos (9U) macro 3076 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100…
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D | stm32wba5mxx.h | 3075 #define DMA_CTR2_SWREQ_Pos (9U) macro 3076 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100…
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D | stm32wba55xx.h | 3075 #define DMA_CTR2_SWREQ_Pos (9U) macro 3076 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100…
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/hal_stm32-latest/stm32cube/stm32h5xx/soc/ |
D | stm32h503xx.h | 3907 #define DMA_CTR2_SWREQ_Pos (9U) macro 3908 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32h523xx.h | 5269 #define DMA_CTR2_SWREQ_Pos (9U) macro 5270 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32h562xx.h | 5712 #define DMA_CTR2_SWREQ_Pos (9U) macro 5713 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32h533xx.h | 5678 #define DMA_CTR2_SWREQ_Pos (9U) macro 5679 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32h573xx.h | 8205 #define DMA_CTR2_SWREQ_Pos (9U) macro 8206 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32h563xx.h | 7796 #define DMA_CTR2_SWREQ_Pos (9U) macro 7797 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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/hal_stm32-latest/stm32cube/stm32u5xx/soc/ |
D | stm32u545xx.h | 6360 #define DMA_CTR2_SWREQ_Pos (9U) macro 6361 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32u535xx.h | 5960 #define DMA_CTR2_SWREQ_Pos (9U) macro 5961 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32u575xx.h | 6359 #define DMA_CTR2_SWREQ_Pos (9U) macro 6360 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32u585xx.h | 6808 #define DMA_CTR2_SWREQ_Pos (9U) macro 6809 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32u595xx.h | 6615 #define DMA_CTR2_SWREQ_Pos (9U) macro 6616 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32u5a5xx.h | 7064 #define DMA_CTR2_SWREQ_Pos (9U) macro 7065 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32u5f7xx.h | 6911 #define DMA_CTR2_SWREQ_Pos (9U) macro 6912 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32u599xx.h | 6903 #define DMA_CTR2_SWREQ_Pos (9U) macro 6904 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32u5g7xx.h | 7360 #define DMA_CTR2_SWREQ_Pos (9U) macro 7361 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32u5f9xx.h | 7031 #define DMA_CTR2_SWREQ_Pos (9U) macro 7032 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/ |
D | stm32h7r3xx.h | 5064 #define DMA_CTR2_SWREQ_Pos (9U) macro 5065 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32h7s7xx.h | 5588 #define DMA_CTR2_SWREQ_Pos (9U) macro 5589 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32h7s3xx.h | 5509 #define DMA_CTR2_SWREQ_Pos (9U) macro 5510 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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D | stm32h7r7xx.h | 5141 #define DMA_CTR2_SWREQ_Pos (9U) macro 5142 #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200…
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