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Searched refs:DMA_CTR1_SSEC (Results 1 – 25 of 38) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_dma.c1415 hdma->Instance->CTR1 |= DMA_CTR1_SSEC; in HAL_DMA_ConfigChannelAttributes()
1419 hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); in HAL_DMA_ConfigChannelAttributes()
1475 …attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_… in HAL_DMA_GetConfigChannelAttributes()
1622 #if defined (DMA_CTR1_SSEC) in DMA_Init()
1623 MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); in DMA_Init()
Dstm32wbaxx_hal_dma_ex.c3533 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; in DMA_List_BuildNode()
3650 if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U) in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_dma.c1427 hdma->Instance->CTR1 |= DMA_CTR1_SSEC; in HAL_DMA_ConfigChannelAttributes()
1431 hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); in HAL_DMA_ConfigChannelAttributes()
1487 …attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_… in HAL_DMA_GetConfigChannelAttributes()
1635 #if defined (DMA_CTR1_SSEC) in DMA_Init()
1636 MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); in DMA_Init()
Dstm32h5xx_hal_dma_ex.c3723 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; in DMA_List_BuildNode()
3963 if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U) in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_dma.c410 hdma->Instance->CTR1 = hdma->Instance->CTR1 & (0U | DMA_CTR1_DSEC | DMA_CTR1_SSEC); in HAL_DMA_DeInit()
1462 hdma->Instance->CTR1 |= DMA_CTR1_SSEC; in HAL_DMA_ConfigChannelAttributes()
1466 hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); in HAL_DMA_ConfigChannelAttributes()
1521 …attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_… in HAL_DMA_GetConfigChannelAttributes()
1743 MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); in DMA_Init()
Dstm32n6xx_hal_dma_ex.c3743 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; in DMA_List_BuildNode()
3983 if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U) in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dma.c1420 hdma->Instance->CTR1 |= DMA_CTR1_SSEC; in HAL_DMA_ConfigChannelAttributes()
1424 hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); in HAL_DMA_ConfigChannelAttributes()
1479 …attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_… in HAL_DMA_GetConfigChannelAttributes()
1624 MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); in DMA_Init()
Dstm32u5xx_hal_dma_ex.c3724 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; in DMA_List_BuildNode()
3962 if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U) in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h722 #define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
1473 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); in LL_DMA_ConfigChannelSecure()
1566 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); in LL_DMA_EnableChannelSrcSecure()
1588 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); in LL_DMA_DisableChannelSrcSecure()
1612 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) in LL_DMA_IsEnabledChannelSrcSecure()
1613 == (DMA_CTR1_SSEC)) ? 1UL : 0UL); in LL_DMA_IsEnabledChannelSrcSecure()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h902 #define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
2112 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); in LL_DMA_ConfigChannelSecure()
2205 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); in LL_DMA_EnableChannelSrcSecure()
2227 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); in LL_DMA_DisableChannelSrcSecure()
2251 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) in LL_DMA_IsEnabledChannelSrcSecure()
2252 == (DMA_CTR1_SSEC)) ? 1UL : 0UL); in LL_DMA_IsEnabledChannelSrcSecure()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h912 #define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
2045 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); in LL_DMA_ConfigChannelSecure()
2168 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); in LL_DMA_EnableChannelSrcSecure()
2198 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); in LL_DMA_DisableChannelSrcSecure()
2229 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) in LL_DMA_IsEnabledChannelSrcSecure()
2230 == (DMA_CTR1_SSEC)) ? 1UL : 0UL); in LL_DMA_IsEnabledChannelSrcSecure()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h947 #define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
2604 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); in LL_DMA_ConfigChannelSecure()
2727 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); in LL_DMA_EnableChannelSrcSecure()
2757 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); in LL_DMA_DisableChannelSrcSecure()
2788 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) in LL_DMA_IsEnabledChannelSrcSecure()
2789 == (DMA_CTR1_SSEC)) ? 1UL : 0UL); in LL_DMA_IsEnabledChannelSrcSecure()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2278 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
Dstm32wba52xx.h2863 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
Dstm32wba54xx.h3046 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
Dstm32wba5mxx.h3046 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
Dstm32wba55xx.h3046 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h5240 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
Dstm32h562xx.h5683 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
Dstm32h533xx.h5649 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
Dstm32h573xx.h8176 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
Dstm32h563xx.h7767 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6331 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
Dstm32u535xx.h5931 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro
Dstm32u575xx.h6330 #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security a… macro

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