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Searched refs:DMA_CTR1_SDW_LOG2 (Results 1 – 25 of 48) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h787 #define LL_DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source Data Width : DoubleWord */
1938 …DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration… in LL_DMA_ConfigTransfer()
2782 …(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, in LL_DMA_SetSrcDataWidth()
2817 …(DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); in LL_DMA_GetSrcDataWidth()
Dstm32h7rsxx_hal_dma.h443 #define DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source data width : DoubleWord */
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h1415 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2171 …(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, in LL_DMA_SetSrcDataWidth()
2197 …(DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); in LL_DMA_GetSrcDataWidth()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h811 #define LL_DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source Data Width : DoubleWord */
2360 …DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration… in LL_DMA_ConfigTransfer()
3598 …(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, in LL_DMA_SetSrcDataWidth()
3633 …(DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); in LL_DMA_GetSrcDataWidth()
Dstm32n6xx_hal_dma.h668 #define DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source data width : DoubleWord */
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h2054 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2811 …(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, in LL_DMA_SetSrcDataWidth()
2837 …(DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); in LL_DMA_GetSrcDataWidth()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h1970 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2989 …(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, in LL_DMA_SetSrcDataWidth()
3023 …(DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); in LL_DMA_GetSrcDataWidth()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim.c4696 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; in HAL_TIM_DMABurst_WriteStart()
5151 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; in HAL_TIM_DMABurst_ReadStart()
Dstm32u5xx_hal_dma_ex.c3950 …SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim.c4696 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; in HAL_TIM_DMABurst_WriteStart()
5151 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; in HAL_TIM_DMABurst_ReadStart()
Dstm32h5xx_hal_dma_ex.c3951 …SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_tim.c4687 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; in HAL_TIM_DMABurst_WriteStart()
5140 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; in HAL_TIM_DMABurst_ReadStart()
Dstm32n6xx_hal_dma_ex.c3971 …SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_tim.c4696 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; in HAL_TIM_DMABurst_WriteStart()
5151 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; in HAL_TIM_DMABurst_ReadStart()
Dstm32wbaxx_hal_dma_ex.c3637 …SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_tim.c4687 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; in HAL_TIM_DMABurst_WriteStart()
5140 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; in HAL_TIM_DMABurst_ReadStart()
Dstm32h7rsxx_hal_dma_ex.c3911 …SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2256 #define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary log… macro
Dstm32wba52xx.h2841 #define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary log… macro
Dstm32wba54xx.h3024 #define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary log… macro
Dstm32wba5mxx.h3024 #define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary log… macro
Dstm32wba55xx.h3024 #define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary log… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3862 #define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary log… macro
Dstm32h523xx.h5218 #define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary log… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6309 #define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary log… macro

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