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Searched refs:DMA_CTR1_PAM_Pos (Results 1 – 25 of 31) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2265 #define DMA_CTR1_PAM_Pos (11U) macro
2266 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
2268 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
2269 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32wba52xx.h2850 #define DMA_CTR1_PAM_Pos (11U) macro
2851 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
2853 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
2854 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32wba54xx.h3033 #define DMA_CTR1_PAM_Pos (11U) macro
3034 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
3036 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
3037 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32wba5mxx.h3033 #define DMA_CTR1_PAM_Pos (11U) macro
3034 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
3036 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
3037 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32wba55xx.h3033 #define DMA_CTR1_PAM_Pos (11U) macro
3034 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
3036 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
3037 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3871 #define DMA_CTR1_PAM_Pos (11U) macro
3872 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
3874 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
3875 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32h523xx.h5227 #define DMA_CTR1_PAM_Pos (11U) macro
5228 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
5230 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
5231 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32h562xx.h5670 #define DMA_CTR1_PAM_Pos (11U) macro
5671 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
5673 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
5674 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32h533xx.h5636 #define DMA_CTR1_PAM_Pos (11U) macro
5637 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
5639 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
5640 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32h573xx.h8163 #define DMA_CTR1_PAM_Pos (11U) macro
8164 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
8166 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
8167 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32h563xx.h7754 #define DMA_CTR1_PAM_Pos (11U) macro
7755 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
7757 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
7758 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6318 #define DMA_CTR1_PAM_Pos (11U) macro
6319 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
6321 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
6322 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32u535xx.h5918 #define DMA_CTR1_PAM_Pos (11U) macro
5919 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
5921 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
5922 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32u575xx.h6317 #define DMA_CTR1_PAM_Pos (11U) macro
6318 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
6320 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
6321 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32u585xx.h6766 #define DMA_CTR1_PAM_Pos (11U) macro
6767 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
6769 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
6770 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32u595xx.h6573 #define DMA_CTR1_PAM_Pos (11U) macro
6574 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
6576 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
6577 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32u5a5xx.h7022 #define DMA_CTR1_PAM_Pos (11U) macro
7023 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
7025 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
7026 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32u5f7xx.h6869 #define DMA_CTR1_PAM_Pos (11U) macro
6870 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
6872 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
6873 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32u599xx.h6861 #define DMA_CTR1_PAM_Pos (11U) macro
6862 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
6864 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
6865 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32u5g7xx.h7318 #define DMA_CTR1_PAM_Pos (11U) macro
7319 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
7321 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
7322 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32u5f9xx.h6989 #define DMA_CTR1_PAM_Pos (11U) macro
6990 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
6992 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
6993 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5025 #define DMA_CTR1_PAM_Pos (11U) macro
5026 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
5028 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
5029 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32h7s7xx.h5549 #define DMA_CTR1_PAM_Pos (11U) macro
5550 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
5552 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
5553 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32h7s3xx.h5470 #define DMA_CTR1_PAM_Pos (11U) macro
5471 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
5473 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
5474 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
Dstm32h7r7xx.h5102 #define DMA_CTR1_PAM_Pos (11U) macro
5103 #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 …
5105 #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
5106 #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */

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