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Searched refs:DMA_CTR1_PAM (Results 1 – 25 of 41) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h1415 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2024 …Y_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, in LL_DMA_SetDataAlignment()
2050 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); in LL_DMA_GetDataAlignment()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h2054 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2664 …Y_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, in LL_DMA_SetDataAlignment()
2690 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); in LL_DMA_GetDataAlignment()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h1970 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2791 …Y_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, in LL_DMA_SetDataAlignment()
2826 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); in LL_DMA_GetDataAlignment()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h1938 …DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration… in LL_DMA_ConfigTransfer()
2586 …Y_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, in LL_DMA_SetDataAlignment()
2620 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); in LL_DMA_GetDataAlignment()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h2360 …DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration… in LL_DMA_ConfigTransfer()
3402 …Y_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, in LL_DMA_SetDataAlignment()
3436 …BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); in LL_DMA_GetDataAlignment()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_dma_ex.c3267 MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), in HAL_DMAEx_ConfigDataHandling()
3961 …DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_dma_ex.c3251 …G(hdma->Instance->CTR1, (DMA_CTR1_DWX | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), in HAL_DMAEx_ConfigDataHandling()
3921 …DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dma_ex.c3268 MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), in HAL_DMAEx_ConfigDataHandling()
3960 …DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_dma_ex.c3198 MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), in HAL_DMAEx_ConfigDataHandling()
3648 …DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_dma_ex.c3287 …G(hdma->Instance->CTR1, (DMA_CTR1_DWX | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), in HAL_DMAEx_ConfigDataHandling()
3981 …DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; in DMA_List_GetNodeConfig()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2267 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32wba52xx.h2852 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32wba54xx.h3035 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32wba5mxx.h3035 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32wba55xx.h3035 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3873 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32h523xx.h5229 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32h562xx.h5672 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32h533xx.h5638 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6320 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32u535xx.h5920 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32u575xx.h6319 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5027 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32h7s7xx.h5551 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro
Dstm32h7s3xx.h5472 #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / … macro

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